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| 1. general description the pca8538 is a fully featured chip-on-glass (cog) 1 liquid crystal display (lcd) driver, designed for high-contrast vertical a lignment (va) lcd with mu ltiplex rates up to 1:9. it generates the drive signals for a static or multiplexed lcd containing up to 9 backplanes, 102 segments, and up to 918 elements. the pca8538 features an internal charge pump with internal capacitors for on-chip generation of the lcd driving voltage. to ensure an optimal and stable contrast over t he full temperature range, the pca8538 offers a programmable temperature compensation of the lcd supply voltage. the pca8538 can be easily controlled by a microc ontroller through either the two-line i 2 c-bus or a four-line bidirectional spi-bus. for a selection of nxp lcd segment drivers, see table 62 on page 102 . 2. features and benefits ? aec q100 grade 2 compliant for automotive applications ? low power consumption ? extended operating temperature range from ? 40 ? c to +105 ? c ? 102 segments and 9 backplanes allowing to drive: ? up to 114 7-segment numeric characters ? up to 57 14-segment alphanumeric characters ? any graphics of up to 918 elements ? 918-bit ram for display data storage ? two sets of backplane outputs providing hi gher flexibility for optimal cog layout configurations ? up to 4 chips can be cascaded to drive larger displays with an internally generated or externally supplied v lcd ? selectable backplane drive configuration: stat ic, 2, 4, 6, 8, or 9 backplane multiplexing ? lcd supply voltage ? programmable internal charge pump for on-chip lcd voltage generation up to 5 ? v dd2 ? external lcd voltage su pply possible as well ? selectable 400 khz i 2 c-bus or 6.5 mhz spi-bus interface ? selectable linear temperature compensation of v lcd ? selectable display bias configuration ? wide range for digital and analog power supply: from 2.5 v to 5.5 v pca8538 automotive 102 x 9 chip-on-glass lcd segment driver rev. 3 ? 25 november 2013 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 21 on page 105 .
pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 2 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver ? wide lcd voltage range from 4.0 v for low threshold lcds up to 12.0 v for high threshold twisted nematic and ve rtical alignment (va) displays ? display memory bank switching in st atic, duplex, and quadruplex drive modes ? programmable frame frequency in the range of 45 hz to 300 hz; factory calibrated with a tolerance of ? 3 hz (at 80 hz) ? selectable inversion scheme for lcd driving waveforms: frame or n-line inversion ? diagnostic features for status monitoring ? integrated temperature sensor with temperature readout ? on chip calibration of intern al oscillator frequency and v lcd ? laser marking at the back-side of the die for traceabilit y of the lot number, wafer number, and die position on the wafer 3. applications ? automotive ? instrument clusters ? climate control ? car entertainment ? car radio ? industrial ? consumer ? medical and health care ? measuring equipment ? machine control systems ? information boards ? white goods ? general-purpose display modules pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 3 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 4. ordering information 4.1 ordering options [1] bump hardness, see table 60 on page 99 . 5. marking [1] the rear side marking has the following meaning: lllllll ? wafer lot number ww ? wafer number xxxxxx ? die identification number table 1. ordering information type number package name description version PCA8538UG bare die 247 bumps PCA8538UG table 2. ordering options product type number sales item (12nc) orderable part number ic revision delivery form PCA8538UG/2da/q1 935301433033 PCA8538UG/2da/q1z 1 chips with bumps [1] in tray table 3. marking codes product type number marking code PCA8538UG/2da/q1 on the active side of the die pc8538-1 on the rear side of the die [1] lllllll ww xxxxxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 4 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 6. block diagram fig 1. block diagram of pca8538 d d d / & ' % , $ 6 * ( 1 ( 5 $ 7 2 5 & / 2 & . 6 ( / ( & 7 $ 1 ' 7 , 0 , 1 * 2 6 & , / / $ 7 2 5 3 2 : ( 5 2 1 5 ( 6 ( 7 & / . 6 & / % $ & . 3 / $ 1 ( 2 8 7 3 8 7 6 ' , 6 3 / $ < & 2 1 7 5 2 / & 2 0 w r & 2 0 6 ( * 0 ( 1 7 2 8 7 3 8 7 6 ' , 6 3 / $ < 5 ( * , 6 7 ( 5 2 8 7 3 8 7 % $ 1 . 6 ( / ( & 7 6 w r 6 3 & $ 5 ( * 8 / $ 7 2 5 9 6 6 9 / & ' 6 ( 1 6 ( & 2 0 0 $ 1 ' ' ( & 2 ' ( 5 : 5 , 7 ( ' $ 7 $ & 2 1 7 5 2 / 9 ' ' 9 ' ' & + $ 5 * ( 3 8 0 3 9 2 / 7 $ * ( 0 8 / 7 , 3 / , ( 5 7 7 7 ( 0 3 ( 5 $ 7 8 5 ( 6 ( 1 6 2 5 7 6 3 , % 8 6 , & % 8 6 , 1 7 ( 5 ) $ & ( & 2 1 7 5 2 / / ( 5 ' $ 7 $ 3 2 , 1 7 ( 5 $ 8 7 2 , 1 & 5 ( 0 ( 1 7 ' , 6 3 / $ < 5 $ 0 , ) 6 6 ' , 6 ' $ , 1 6 $ & ( 6 < 1 & 6 ' $ 2 8 7 9 ' ' 9 6 6 9 6 6 9 / & ' 2 8 7 5 6 7 9 / & ' , 1 6 < 1 & 2 6 & 7 7 7 6 8 % $ ' ' 5 ( 6 6 & 2 8 1 7 ( 5 $ $ 6 $ 6 ' 2 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 5 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 7. pinning information 7.1 pinning viewed from active side. for mechanical details, see figure 64 on page 94 . fig 2. pinning diagram of PCA8538UG \ [ 3 & $ 8 & 2 0 & 2 0 & 2 0 & 2 0 & 2 0 9 / & ' , 1 9 / & ' 6 ( 1 6 ( 9 / & ' 2 8 7 7 7 7 7 9 6 6 9 6 6 9 6 6 7 7 $ $ , ) 6 2 6 & 6 $ 6 $ 9 ' ' 9 ' ' 9 ' ' & ( & / . 6 < 1 & 6 < 1 & 5 6 7 6 ' , 6 ' $ , 1 6 ' $ 2 8 7 6 ' 2 6 & / & 2 0 & 2 0 & 2 0 & 2 0 6 6 6 & 2 0 & 2 0 & 2 0 & 2 0 & 2 0 & 2 0 & 2 0 & 2 0 & 2 0 6 6 6 d d d pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 6 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 7.2 pin description table 4. pin description input or input/output pins must always be at a defined level (v ss or v dd ) unless otherwise specified. symbol pin type description backplane output pins com8 1 to 3, 194, 195 output lcd backplane com7 4, 5, 192, 193 com6 6, 7, 190, 191 com5 8, 9, 188, 189 com4 10, 11, 186, 187 com3 117, 118, 184, 185 com2 119, 120, 182, 183 com1 121, 122, 180, 181 com0 123 to 125, 178, 179 segment output pins s101 126, 127 output lcd segment s100 to s51 128 to 177 s50 to s1 196 to 245 s0 246, 247 v lcd pins vlcdin 12 to 15 supply v lcd input vlcdsense 16 to 18 input v lcd regulation input vlcdout 19 to 22 output v lcd output test pins t4 23 to 25 output not accessible; must be left open t3 26 to 30 input not accessible; must be connected to t5 t5 31, 32 output not accessible; must be connected to t3 t6 33, 34 output not accessible; must be left open t1 58, 59 input not accessible; must be connected to v ss1 t2 60, 61 supply pins vss2 [1] 35 to 44 supply ground supply vss3 [1] 45 to 48 vss1 [1] 49 to 57 vdd1 74 to 78 supply supply voltage 1 (analog and digital) vdd3 79 to 82 supply supply voltage 3 (analog) vdd2 83 to 90 supply supply voltage 2 (charge pump) pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 7 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] the substrate (rear side of the die) is connected to v ss1 and should be electrically isolated. [2] if pin osc is tied to v ss1 , clk is the output pin of the internal oscillator. if pin osc is tied to v dd1 , clk is the input pin for the external oscillator. [3] if cascading is not used, pin must be left floating; for cascading see section 15.2 on page 89 . oscillator, synchronization, addressing, and reset pins clk [2] 93 to 95 input/output internal oscill ator output, external oscillator input osc [2] 68, 69 input clock (internal/external) selector sync1 [3] 96 to 98 input/output charge pump synchro nization for cascaded devices; must not be connected if v lcd is externally supplied sync0 [3] 99 to 101 input/output display synch ronization for cascaded devices rst 102, 103 input active low reset input a0 62, 63 input hardware device address selection for cascading; ? connect to v ss1 for logic 0 ? connect to v dd1 for logic 1 a1 64, 65 bus-related pins spi-bus i 2 c-bus ifs 66, 67 input interface selector input ? connect to v ss1 ? connect to v dd1 sa0 70, 71 input unused; ? connect to v ss1 slave address selector; ? connect to v ss1 for logic 0 ? connect to v dd1 for logic 1 sa1 72, 73 input ce 91, 92 input chip enable input (active low) unused; ? connect to v dd1 sdi/sdain 104 to 106 input spi-bus data input i 2 c-bus serial data input sdaout 107 to 111 output unused; ? must be connected to v ss1 serial data output sdo 112, 113 output spi serial data output unused; ? must be left open scl 114 to 116 input serial clock input serial clock input table 4. pin description ?continued input or input/output pins must always be at a defined level (v ss or v dd ) unless otherwise specified. symbol pin type description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 8 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8. functional description 8.1 commands of pca8538 the pca8538 is controlled by the commands defined in table 5 . remark: any other combinations of operation code bits that are not mentioned in this document may lead to undesired operation modes of pca8538. table 5. commands of pca8538 command name r/w [1] register selection rs[1:0] [2] command bits reference 7 6 5 4 3 2 1 0 general control commands initialize 0 0 0 00111010 section 8.2.1 otp-refresh 0 0 0 11011000 section 8.2.2 device-address 0 0 0 000110a[1:0] section 8.2.3 sync1_pin 0 0 0 1011100oe section 8.2.4 clock-out-ctrl 0 0 0 1101010coe section 8.2.5 read-select 0 0 0 0001110so section 8.2.6 status-readout 1 0 0 td[7:0] section 8.2.7 sr[7:0] clear-reset-flag 0 0 0 00011111 section 8.2.8 charge pump and lcd bias control commands charge-pump-ctrl 0 0 0 1100cpecpc[2:0] section 8.3.1 set-v lcd 0 0 0 010v[8:4] section 8.3.2 0 0 0 0110v[3:0] set-bias-mode 0 0 0 110100b[1:0] section 8.3.3 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 9 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] for further information about the r/w -bit, see table 46 on page 65 . [2] for further information about the register selection bits, see table 46 on page 65 . temperature compensation control commands temperature-ctrl 0 1 0 00000tcetmftme section 8.4.1 tc-slope 0 1 0 00001tsa[2:0] section 8.4.3 0 1 0 00010tsb[2:0] 0 1 0 00011tsc[2:0] 0 1 0 00100tsd[2:0] 0 1 0 00101tse[2:0] 0 1 0 00110tsf[2:0] tc-set 0 1 0 00111t1t[2:0] section 8.4.2 0 1 0 01000t2t[2:0] 0 1 0 01001t3t[2:0] 0 1 0 01010t4t[2:0] display control commands set-mux-mode 0 0 0 00000m[2:0] section 8.5.1 inversion-mode 0 0 0 10110inv[2:0] section 8.5.2 display-ctrl 0 0 0 0011100de section 8.5.3 clock and frame frequency command frame-frequency 0 0 0 111ff[4:0] section 8.6.4 display ram commands write-display-data 0 0 1 db[7:0] section 8.7.1 input-bank-select 0 0 0 00001ib[2:0] section 8.7.2 output-bank-select 0 0 0 00010ob[2:0] data-pointer-x 0 0 0 10000px[6:4] section 8.7.3 0 0 0 1001px[3:0] data-pointer-y 0 0 0 1010000py0 table 5. commands of pca8538 ?continued command name r/w [1] register selection rs[1:0] [2] command bits reference 7 6 5 4 3 2 1 0 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 10 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.2 general control commands 8.2.1 command: initialize this command generates a chip-wide reset by setting all commands to their default values. for further information, see section 8.8 on page 25 . 8.2.2 command: otp-refresh each ic is calibrated during production and te sting of the device in order to achieve the specified accuracy of the v lcd , the frame frequency, and the temperature measurement. this calibration is performed on eprom cells called one time programmable (otp) cells. these cells are read by the device afte r a reset and every time when the initialize command or the otp-refresh command is sent. this command takes approximately 10 ms to finish. 8.2.3 command: device-address the device-address command allows setting the address of the device in a cascaded configuration and corresponds with pins a0 and a1 (see section 15.2 on page 89 ). [1] default value. table 6. initialize command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 0 - 00111010 fixed value table 7. otp-refresh - otp-re fresh command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 0 - 11011000 fixed value table 8. device-address - device address command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 2 - 000110 fixed value 1 to 0 a[1:0] set address 00 [1] master 01 slave 1 10 slave 2 11 slave 3 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 11 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.2.4 command: sync1_pin with the sync1_pin command, the sync1 pin can be configured for using the pca8538 as a single chip or a master in a cascade. if the pca8538 is a slave in a cascade, the command has no effect. [1] default value. 8.2.5 command: clock-out-ctrl when pin clk is configured as an output pin, the clock-out-ctrl command enables or disables the clock ou tput on pin clk ( section 8.6.1 on page 21 ). [1] default value. table 9. sync1_pin - sync1 pin conf iguration command bit description this command has no effect if the pca8538 is a slave in a cascade. bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 1 - 1011100 fixed value 0oe sync1 pin configuration 0 [1] pin sync1 is an output; gated to 0 v; to be used when pca8538 is a single chip 1 pin sync1 is an output; providing the synchronization signal; to be used when pca8538 is a master in a cascade table 10. clock-out-ctrl - clk pin input/output switch command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 1 - 1101010 fixed value 0coe control pin clk 0 [1] clock signal not available on pin clk; pin clk is in 3-state 1 clock signal available on pin clk pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 12 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.2.6 command: read-select the read-select command allows choosing to readout the temperature or the device status. [1] default value. 8.2.7 command: status-readout the status-readout command offers to readout some status bits of the pca8538. these bits indicate the status of the device at the moment of reading. table 11. read-select - status read select command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 1 - 0001110 fixed value 0so readout 0 [1] temperature; the status-readout command allows to readout the temperat ure td[7:0], see ta b l e 1 2 1 device status: the status-readout command allows to readout some information about the status of the device, see ta b l e 1 2 table 12. status-readout - status and temperature read command bit description for this command, bit r/w has to be set logic 1. bit symbol value description -r/w 1 fixed value - rs[1:0] 00 fixed value temperature readout if so = 0 (see table 11 ) 7 to 0 td[7:0] 00000000 to 11111111 [1] temperature readout (see section 8.10.4.1 on page 40 ) device status readout if so = 1 (see table 11 ) 7sr7 display status (see table 22 on page 20 ) 0 [1] display is disabled 1 display is enabled 6sr6 charge pump switching status (status of bit cpe, see table 14 on page 14 ) 0 [1] charge pump disabled 1 charge pump enabled 5sr5 charge pump charge status 0 [1] charge pump has not reached programmed value 1 charge pump has reached programmed value pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 13 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] default value. [2] the flag is set whenever a reset occurs, induced by rst pin, power-on reset (por), or initialize command. after power-on, the flag is set and should be cleared for reset monitoring. some bits of the status-readout command hav e a certain probability of being changed by an emc/esd event. for example, an em c/esd event can cause a change of the hard-wired settings of sa1 or sa0. therefore sr [3:0] can help to detect if an emc/esd event has occurred which has caused the change of a bit. in environments where emc/esd events may occur, it could be helpful to compare the result of the status-readout command with the initial bit settings periodically. 8.2.8 command: clear-reset-flag the clear-reset-flag command clea rs the reset flag sr4, see ta b l e 1 2 . 4sr4 reset status flag 0 no reset has occurred since the reset status flag was cleared last time 1 [1] reset has occurred since the reset status flag was cleared last time [2] 3 to 0 sr[3:0] emc detection 01sa1sa0 pre-defined code for emc detection when i 2 c interface is used 0101 pre-defined code for emc detection when spi interface is used table 12. status-readout - status and temperature read command bit description ?continued for this command, bit r/w has to be set logic 1. bit symbol value description table 13. clear-reset-flag - clear-r eset-flag command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 0 - 00011111 fixed value pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 14 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.3 charge pump and lcd bias control commands 8.3.1 command: charge-pump-ctrl the charge-pump-ctrl command enables or disables the internal v lcd generation and controls the charge pump voltage multiplier settings. [1] default value. 8.3.2 command: set-v lcd the set-v lcd command allows setting the lcd voltage. [1] default value. table 14. charge-pump-ctrl - charge pump control command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 4 - 1100 fixed value 3cpe charge pump status 0 [1] charge pump disabled; no internal v lcd generation; external supply of v lcd 1 charge pump enabled; internal v lcd generation; no external supply of v lcd 2 to 0 cpc[2:0] charge pump voltage multiplier setting 000 [1] v lcd = 2 ? v dd2 001 v lcd = 3 ? v dd2 010 v lcd = 4 ? v dd2 011 v lcd = 5 ? v dd2 100 to 111 v lcd = v dd2 (direct mode) table 15. set-v lcd - set-v lcd command bit description bit symbol value description set-v lcd -msb -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 5 - 010 fixed value 4 to 0 v[8:4] set v lcd msb 00000 [1] to 11111 the 5 most significant bits of v[8:0] set-v lcd -lsb -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 4 - 0110 fixed value 3 to 0 v[3:0] set v lcd lsb 0000 [1] to 1111 the 4 least significant bits of v[8:0] pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 15 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver a value of 0h corresponds to v lcd = 4 v and values equal or higher than 10ch correspond to v lcd = 12 v without temperature compensation. every lsb change corresponds to a v lcd programming step of 0.03 v. for further information, see equation 2 on page 35 and section 8.10.3 on page 34 . 8.3.3 command: set-bias-mode [1] default value. table 16. set-bias-mode - set bias mode command bit description this command is not applicabl e for the static drive mode. bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 2 - 110100 fixed value 1 to 0 b[1:0] set bias mode 00 [1] , 01 1 4 bias 11 1 3 bias 10 1 2 bias pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 16 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.4 temperature compensation control commands 8.4.1 command: temperature-ctrl the temperature-ctrl command enables or di sables the temperature measurement block and the temperature compensation of v lcd (see section 8.10.4 on page 40 ). [1] default value. [2] the unfiltered digital value of td[7:0] is immediately available for the readout and v lcd compensation. table 17. temperature-ctrl - temperature m easurement control command bit description for this command, the register selection bits have to be set rs[1:0] = 10. bit symbol value description -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00000 fixed value 2tce temperature compensation control 0 [1] temperature compensation of v lcd disabled 1 temperature compensation of v lcd enabled 1tmf temperature measurement filter 0 [1] digital temperature filter disabled [2] 1 digital temperature filter enabled 0tme temperature measurement control 0 [1] temperature measurement disabled; no temperature readout possible 1 temperature measurement enabled; temperature readout possible pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 17 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.4.2 command: tc-set the tc-set command allows defining six temperature intervals in the operating temperature range from ?40 ? c to +105 ? c. for each of the temperature intervals, the tc-slope command (see section 8.4.3 ) allows setting the temperature coefficient of v lcd . [1] default value. table 18. tc-set - v lcd temperature compensation set command bit description for this command, the register selection bits have to be set rs[1:0] = 10. bit symbol value description tc-set-1 -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00111 fixed value 2 to 0 t1t[2:0] 000 [1] to 111 see table 33 on page 42 tc-set-2 -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 01000 fixed value 2 to 0 t2t[2:0] 000 [1] to 111 see table 33 on page 42 tc-set-3 -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 01001 fixed value 2 to 0 t3t[2:0] 000 [1] to 111 see table 33 on page 42 tc-set-4 -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 01010 fixed value 2 to 0 t4t[2:0] 000 [1] to 111 see table 33 on page 42 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 18 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.4.3 command: tc-slope the tc-slope command allows setting the temperature coefficients of v lcd corresponding to six temperature intervals defined by the tc-set command. [1] default value. table 19. tc-slope - v lcd temperature compensation slope command bit description for this command, the register selection bits have to be set rs[1:0] = 10. bit symbol value description tc-slope-a -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00001 fixed value 2 to 0 tsa[2:0] 000 [1] to 111 see table 34 on page 43 tc-slope-b -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00010 fixed value 2 to 0 tsb[2:0] 000 [1] to 111 see table 34 on page 43 tc-slope-c -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00011 fixed value 2 to 0 tsc[2:0] 000 [1] to 111 see table 34 on page 43 tc-slope-d -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00100 fixed value 2 to 0 tsd[2:0] 000 [1] to 111 see table 34 on page 43 tc-slope-e -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00101 fixed value 2 to 0 tse[2:0] 000 [1] to 111 see table 34 on page 43 tc-slope-f -r/w 0 fixed value - rs[1:0] 10 fixed value 7 to 3 - 00110 fixed value 2 to 0 tsf[2:0] 000 [1] to 111 see table 34 on page 43 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 19 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.5 display control commands 8.5.1 command: set-mux-mode the set-mux-mode command allows setting the multiplex drive mode. [1] default value. 8.5.2 command: inversion-mode the inversion-mode command allows changing the drive scheme inversion mode. the waveforms used to drive lcd displays (see figure 25 on page 47 to figure 33 on page 55 ) inherently produce a dc voltage across the display cell. the pca8538 compensates for the dc voltage by inverting the waveforms on alternate frames or alternate lines. the choice of the compensa tion method is determi ned with inv[2:0] in ta b l e 2 1 . [1] default value. table 20. set-mux-mode - set multiplex drive mode comman d bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 3 - 00000 fixed value 2 to 0 m[2:0] set multiplex drive mode 000 [1] 1:9 multiplex drive mode 001 010 011 1:8 multiplex drive mode 100 1:6 multiplex drive mode 101 1:4 multiplex drive mode 110 1:2 multiplex drive mode 111 static table 21. inversion-mode - inversion mode command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 3 - 10110 fixed value 2 to 0 inv[2:0] set inversion mode 000 [1] frame inversion mode 001 1-line inversion mode 010 2-line inversion mode 011 3-line inversion mode 100 4-line inversion mode 101 5-line inversion mode 110 6-line inversion mode 111 7-line inversion mode pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 20 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.5.2.1 line inversion mode (driving scheme a) in line inversion mode, the dc value is compensated every n th line. changing the inversion mode to line inversio n mode reduces the possibility for flickering but increases the power consumption (see example waveforms in figure 25 on page 47 to figure 32 on page 54 ) 8.5.2.2 frame inversion mode (driving scheme b) in frame inversion mode, the dc value is co mpensated across two frames and not within one frame (see example waveform in figure 33 on page 55 ). changing the inversion mode to frame inversion reduces the power consumption, therefore it is useful when power consumption is a key point in the application. frame inversion may not be suitable for all applications. the rms voltage across a segment is better defined, however since the switching frequency is reduced there is possibility for flicker to occur. 8.5.3 command: display-ctrl the display-ctrl command enables or disables the display. [1] default value. table 22. display-ctrl - display on an d off switch command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 1 - 0011100 fixed value 0de display control 0 [1] display disabled 1 display enabled pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 21 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.6 clock and frame frequency command 8.6.1 oscillator the internal logic and lcd drive signals of the pca8538 are timed by the clock frequency f clk , which is either internally generated by an on-chip oscillator ci rcuit or externally supplied. the clock frequency f clk determines the internal data flow of the device that includes the transfer of display data from the display ram to the display segment outputs and the generation of the lcd frame frequency. 8.6.2 external clock when an external clock is used, the input pin osc must be connected to v dd1 . the clock must be supplied to the clk pin and must have an amplitude equal to the v dd1 voltage supplied to the chip and be referenced to v ss1 . remark: if an external clock is used, then this clock signal must always be supplied to the device. removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. removal of the clock is possibl e when following the correct procedures as described in section 8.8.4 on page 29 . 8.6.3 internal clock in applications where the internal clock is used, the input pin osc must be connected to v ss1 . it is possible to make the clock frequency available on pin clk by setting bit coe logic 1 (see table 10 on page 11 ). if pin clk is not used, it should be left open. at power-on the signal at pin clk is disabled and pin clk is in 3-state. 8.6.4 command: frame-frequency with this command the clock and frame fr equency can be programmed when using the internal clock. the duty ratio of the clock output may change when choosing different values for the frame frequency (see table 24 ). the lcd frame frequency is derived from the clock frequency by a fixed division (see equation 1 ). (1) table 23. frame-frequency - frame freque ncy select command bit description bit symbol value description -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 5 - 111 fixed value 4 to 0 ff[4:0] see ta b l e 2 4 clock and frame frequency (hz) f fr f clk 144 -------- - = pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 22 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver the frame-frequency command allows configuring the frame frequency in the range of 45 hz to 300 hz with steps of ? 5 hz from 45 hz to 100 hz ? 10 hz from 100 hz to 300 hz the default frame frequency of 80 hz is factory calibrated with a tolerance of ? 3 hz at 25 ? c. [1] default value. table 24. clock and frame frequency values duty cycle definition: % high-le vel time : % low-level time. ff[4:0] frame frequency (hz) clock frequency (hz) typical duty cycle (%) [1] 00000 45 6472 29 : 71 00001 50 7200 20 : 80 00010 55 7945 12 : 88 00011 60 8662 4 : 96 00100 65 9366 48 : 52 00101 70 10105 44 : 56 00110 75 10766 41 : 59 00111 [1] 80 11520 36 : 64 01000 85 12255 32 : 68 01001 90 12944 29 : 71 01010 95 13714 24 : 76 01011 100 14400 20 : 80 01100 110 15781 13 : 87 01101 120 17194 5 : 95 01110 130 18581 49 : 51 01111 140 20211 44 : 56 10000 150 21736 40 : 60 10001 160 23040 36 : 64 10010 170 24511 32 : 68 10011 180 26182 28 : 72 10100 190 27429 24 : 76 10101 200 28800 20 : 80 10110 210 30316 16 : 84 10111 220 32000 12 : 88 11000 230 32914 9 : 91 11001 240 34909 4 : 96 11010 250 36000 50 : 50 11011 260 37161 49 : 51 11100 270 38400 47 : 53 11101 280 39724 45 : 55 11110 290 41143 43 : 57 11111 300 42667 41 : 59 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 23 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.7 display ram commands 8.7.1 command: write-display-data the write-display-data command writes data byte-wise to the ram. after power-on reset (por) the ram content is random and should be brought to a defined status by clearing it (setting it logic 0). more information about the display ram can be found in section 8.14 on page 57 . 8.7.2 bank select commands for multiplex drive modes 1:4, 1:2, and static drive mode, it is possible to write data to one area of the ram while displaying from another. these areas are named as ram banks. input and output banks can be set independently from one another with the input-bank-select and the output-bank-sele ct command. more information about ram bank switching can be found in section 8.14.3 on page 62 . 8.7.2.1 command: input-bank-select [1] default value. table 25. write-display-data - write display data command bit description for this command, the register selection bits have to be set rs[1:0] = 01. bit symbol value description -r/w 0 fixed value - rs[1:0] 01 fixed value 7 to 0 db[7:0] 00000000 to 11111111 writing data byte-wise to ram table 26. input-bank-select - input ba nk select command bit description this command is not applicable for mu ltiplex drive mode 1:6, 1:8, and 1:9. bit symbol value description -r/w 0 fixed value - r/w - rs[1:0] 00 fixed value - rs[1:0] 7 to 3 - 00001 fixed value 2 to 0 ib[2:0] selects ram bank to write to static drive mode 1:2 drive mode 1:4 drive mode 000 [1] bank 0: ram-row 0 bank 0: ram-rows 0 and 1 bank 0: ram-rows 0, 1, 2, and 3 001 bank 1: ram-row 1 010 bank 2: ram-row 2 bank 2: ram-rows 2 and 3 011 bank 3: ram-row 3 100 bank 4: ram-row 4 bank 4: ram-rows 4 and 5 bank 4: ram-rows 4, 5, 6, and 7 101 bank 5: ram-row 5 110 bank 6: ram-row 6 bank 6: ram-rows 6 and 7 111 bank 7: ram-row 7 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 24 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.7.2.2 command: output-bank-select [2] default value. 8.7.3 commands: data-pointer-x and data-pointer-y the data-pointer-x and data-pointer-y co mmands define the display ram address where the following display data will be sent to. [1] default value. table 27. output-bank-select - output bank select command bit description this command is not applicable for mu ltiplex drive mode 1:6, 1:8, and 1:9. bit symbol value description -r/w 0 fixed value - r/w - rs[1:0] 00 fixed value - rs[1:0] 7 to 3 - 00010 fixed value 2 to 0 ob[2:0] selects ram bank to read from to the lcd static drive mode 1:2 drive mode 1:4 drive mode 000 [2] bank 0: ram-row 0 bank 0: ram-rows 0 and 1 bank 0: ram-rows 0, 1, 2, and 3 001 bank 1: ram-row 1 010 bank 2: ram-row 2 bank 2: ram-rows 2 and 3 011 bank 3: ram-row 3 100 bank 4: ram-row 4 bank 4: ram-rows 4 and 5 bank 4: ram-rows 4, 5, 6, and 7 101 bank 5: ram-row 5 110 bank 6: ram-row 6 bank 6: ram-rows 6 and 7 111 bank 7: ram-row 7 table 28. data-pointer-x and data-pointer-y - set data pointer command bit description bit symbol value description data-pointer-x-msb: px[6:4] -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 3 - 10000 fixed value 2 to 0 px[6:4] 000 [1] to 111 3-bit binary value data-pointer-x-lsb: px[3:0] -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 4 - 1001 fixed value 3 to 0 px[3:0] 0000 [1] to 1111 4-bit binary value data-pointer-y: py0 -r/w 0 fixed value - rs[1:0] 00 fixed value 7 to 1 - 1010000 fixed value 0 py0 0 [1] to 1 1-bit binary value pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 25 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.8 start-up and shut-down 8.8.1 power-on reset (por) at power-on, the pca8538 resets to the following starting conditions: 1. all backplane and segment outputs are set to v ss1 . 2. selected drive mode is: 1:9 with 1 4 bias. 3. input and output bank selectors are reset. 4. the interface is initialized. 5. the data pointer is cleared (set logic 0). 6. the internal oscillator is disabled. 7. temperature measurement is disabled. 8. temperature filter is disabled. 9. the internal v lcd voltage generation is disabled. the charge pump is switched off. 10. the v lcd temperature compensation is disabled. 11. the display is disabled. the reset state is as shown in ta b l e 2 9 . table 29. reset state of pca8538 command name command bits 7 6 5 4 3 2 1 0 general control commands device-address 00011000 sync1_pin 10111000 clock-out-ctrl 1 1 0 1 0 1 0 0 read-select 00011100 status-readout 1 1 1 1 1 1 1 1 0001010/sa11/sa0 charge pump and lcd bias control commands charge-pump-ctrl 1 1 0 0 0 0 0 0 set-v lcd 01000000 01100000 set-bias-mode 1 1 0 1 0 0 0 0 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 26 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver remarks: 1. do not transfer data for at least 1 ms after a power-on to allow the reset action to complete. 2. the first command sent to the device afte r the power-on event must be the initialize command (see section 8.2.1 on page 10 ). 3. after power-on reset (por) and before enabling the display, the ram content should be brought to a defined status ? by clearing it (setting it all logic 0) or ? by writing meaningful content (for example, a graphic) otherwise unwanted display artifacts may appear on the display. 8.8.2 reset pin function the reset pin of the pca8538 resets all t he registers to their default state (see ta b l e 2 9 ). the ram contents remain unchanged. after the reset signal is remo ved, the pca8538 will behave in the same manner as at por. see section 8.8.1 for details. temperature compensation control commands temperature-ctrl 00000000 tc-slope-a 00001000 tc-slope-b 00010000 tc-slope-c 00011000 tc-slope-d 00100000 tc-slope-e 00101000 tc-slope-f 00110000 tc-set-1 00111000 tc-set-2 01000000 tc-set-3 01001000 tc-set-4 01010000 display control commands set-mux-mode 00000000 inversion-mode 10110000 display-ctrl 00111000 clock and frame frequency command frame-frequency 1 1 1 0 0 1 1 1 display ram commands input-bank-select 0 0 0 0 1 0 0 0 output-bank-select 00010000 data-pointer-x-msb 1 0 0 0 0 0 0 0 data-pointer-x-lsb 10010000 data-pointer-y 10100000 table 29. reset state of pca8538 ?continued command name command bits 7 6 5 4 3 2 1 0 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 27 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.8.3 recommended start-up sequences this section describes how to proceed with the initialization of the chip in different application modes. when using the internal v lcd generation, the display must not be enabled before the generation of v lcd with the internal charge pump is completed. otherwise unwanted display artifacts may appear on the display. (1) this time depends on the external capacitor on the v lcd pins. for a capacitor of 100 nf a delay of about 55 ms to 65 ms is expected. fig 3. recommended start-up sequence when using the internal charge pump and the internal clock signal fig 4. recommended start-up sequence when using an external supplied v lcd and the internal clock signal : d l w p v 6 7 $ 5 7 3 r z h u r q 9 ' ' w r 9 ' ' d w w k h v d p h w l p h d d d 6 h w p x o w l s o l f d w l r q i d f w r u i r u f k d u j h s x p s d q g h q d e o h l w : d l w w l o o 9 / & ' u h d f k h v s u r j u d p p h g y d o x h : u l w h 5 $ 0 f r q w h q w w r e h g l v s o d \ h g d q g h q d e o h w k h g l v s o d \ 6 7 2 3 , q l w l d o l ] h f r p p d q g 6 h w w k h g h v l u h g 9 / & ' y d o x h : d l w p v 6 7 $ 5 7 3 r z h u r q 9 ' ' w r 9 ' ' d q g 9 / & ' d w w k h v d p h w l p h d d d : u l w h 5 $ 0 f r q w h q w w r e h g l v s o d \ h g d q g h q d e o h w k h g l v s o d \ 6 7 2 3 , q l w l d o l ] h f r p p d q g pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 28 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver (1) alternatively, the external clock signal can be applied after the generation of the v lcd voltage. (2) this time depends on the external capacitor on the v lcd pins. for a capacitor of 100 nf a delay of about 55 ms to 65 ms is expected. fig 5. recommended start-up sequence when using the internal charge pump and an external clock signal fig 6. recommended start-up sequence when using an external supplied v lcd and an external clock signal : d l w p v 6 7 $ 5 7 3 r z h u r q 9 ' ' w r 9 ' ' d w w k h v d p h w l p h , q l w l d o l ] h f r p p d q g d d d 6 h w w k h g h v l u h g 9 / & ' y d o x h : d l w w l o o 9 / & ' u h d f k h v s u r j u d p p h g y d o x h : u l w h 5 $ 0 f r q w h q w w r e h g l v s o d \ h g d q g h q d e o h w k h g l v s o d \ 6 7 2 3 $ s s o \ h [ w h u q d o f o r f n v l j q d o w r s l q & / . 6 h w p x o w l s o l f d w l r q i d f w r u i r u f k d u j h s x p s d q g h q d e o h l w : d l w p v 6 7 $ 5 7 d d d : u l w h 5 $ 0 f r q w h q w w r e h g l v s o d \ h g d q g h q d e o h w k h g l v s o d \ 6 7 2 3 $ s s o \ h [ w h u q d o f o r f n v l j q d o w r s l q & / . 3 r z h u r q 9 ' ' w r 9 ' ' d q g 9 / & ' d w w k h v d p h w l p h , q l w l d o l ] h f r p p d q g pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 29 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.8.4 recommended power-down sequences with the following sequences, the pca8538 can be set to a state of minimum power consumption, called power-down mode. (1) if previously enabled. remark: when bits de ( table 22 on page 20 ), cpe ( table 14 on page 14 ) and tme ( table 17 on page 16 ) are logic 0, the internal clock signal is switched off. fig 7. recommended power-down sequence for minimum power-do wn current when using the internal charge pump and the internal clock signal 6 7 $ 5 7 ' l v d e o h g l v s o d \ e \ v h w w l q j e l w ' ( o r j l f d d d 6 7 2 3 ' l v d e o h w h p s h u d w x u h p h d v x u h p h q w e \ v h w w l q j e l w 7 0 ( o r j l f 6 w r s j h q h u d w l r q r i 9 / & ' e \ v h w w l q j e l w & 3 ( o r j l f pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 30 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver (1) if previously enabled. remark: when bits de ( table 22 on page 20 ), cpe ( table 14 on page 14 ) and tme ( table 17 on page 16 ) are logic 0, the internal clock signal is switched off. fig 8. recommended power-down sequence when using an external supplied v lcd and the internal clock signal (1) if previously enabled. fig 9. recommended power-down sequence when using the internal charge pump and an external clock signal 6 7 $ 5 7 ' l v d e o h g l v s o d \ e \ v h w w l q j e l w ' ( o r j l f ' l v d e o h w h p s h u d w x u h p h d v x u h p h q w e \ v h w w l q j e l w 7 0 ( o r j l f d d d 6 7 2 3 6 w r s j h q h u d w l r q r i 9 / & ' e \ v h w w l q j e l w & 3 ( o r j l f 6 7 $ 5 7 ' l v d e o h g l v s o d \ e \ v h w w l q j e l w ' ( o r j l f ' l v d e o h w h p s h u d w x u h p h d v x u h p h q w e \ v h w w l q j e l w 7 0 ( o r j l f d d d 6 7 2 3 6 w r s v x s s o \ r i w k h h [ w h u q d o f o r f n w r s l q & / . pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 31 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver remarks: 1. it is necessary to run the power-down sequence before removing the supplies. depending on the application, care must be taken that no other signals are present at the chip input or output pins when removing the supplies (refer to section 10 on page 72 ). otherwise this may cause unwanted display artifacts. uncontrolled removal of supply voltages will not damage the pca8538. 2. static voltages across the liquid crystal display can build up when the external lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd1 to v dd3 ) is off, or the other way round. this may cause unwanted display artifacts. to avoid such artifacts, external v lcd , v dd1 to v dd3 must be applied or removed together. 3. a clock signal must always be supplied to the device when the device is active. removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. it is recommended to disable the display first and to remove the clock signal afterwards. (1) if previously enabled. fig 10. recommended power-down sequence when using an external supplied v lcd and an external clock signal 6 7 $ 5 7 ' l v d e o h g l v s o d \ e \ v h w w l q j e l w ' ( o r j l f ' l v d e o h w h p s h u d w x u h p h d v x u h p h q w e \ v h w w l q j e l w 7 0 ( o r j l f d d d 6 7 2 3 6 w r s v x s s o \ r i w k h h [ w h u q d o f o r f n w r s l q & / . pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 32 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.9 possible display configurations the display configurations possible with t he pca8538 depend on the number of active backplanes outputs required. a selection of po ssible display configurations is given in ta b l e 3 0 . [1] 7 segment display has 8 elements including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. all the display configurations in table 30 can be implemented in the typical systems shown in figure 12 and figure 13 . fig 11. example of display types suitable for pca8538 table 30. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment [1] 14-segment [2] 9 918 114 57 918 dots (9 ? 102) 8 816 102 51 816 dots (8 ? 102) 6 612 76 38 612 dots (6 ? 102) 4 408 51 25 408 dots (4 ? 102) 2 204 25 12 204 dots (2 ? 102) 1 102 12 6 102 dots (1 ? 102) v h j p h q w z l w k g r w v h j p h q w z l w k g r w d q g d f f h q w d d d g r w p d w u l [ pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 33 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver the host microcontroller maintains the commu nication channel with the pca8538. the only other connections required to complete the system are the power supplies, the v lcd pins, the external capacitors, and the lcd panel selected for the application. the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. external capacitors of 100 nf minimum are re quired on each of the pins vdd1 to vdd3. vdd1 to vdd3 can be connecte d to the same power supply. in this case, a capacitor of 300 nf minimum is required. v dd1 to v dd3 from 2.5 v to 5.5 v. v dd1 to v dd3 can be connected to the same power supply. v ss1 to v ss3 can be connected to the same ground supply. fig 12. typical system configuration if using the internal v lcd generation and i 2 c-bus d d d 3 & $ + 2 6 7 0 , & 5 2 & 2 1 7 5 2 / / ( 5 / & ' 3 $ 1 ( / 8 3 7 2 ( / ( 0 ( 1 7 6 v h j p h q w v e d f n s o d q h v 9 ' ' 5 ? , ) 6 9 ' ' 9 ' ' 6 ' , 6 ' $ , 1 6 ' $ 2 8 7 6 & / w u & e 9 6 6 9 ' ' $ $ 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 ' ' 9 ' ' 9 / & ' 2 8 7 9 / & ' 6 ( 1 6 ( 9 / & ' , 1 v dd1 to v dd3 from 2.5 v to 5.5 v. fig 13. typical system configuration if using the external v lcd and spi-bus d d d 3 & $ + 2 6 7 0 , & 5 2 & 2 1 7 5 2 / / ( 5 / & ' 3 $ 1 ( / 8 3 7 2 ( / ( 0 ( 1 7 6 v h j p h q w v e d f n s o d q h v 9 ' ' 6 & / 9 ' ' 9 ' ' 6 ' , 6 ' $ , 1 6 ' 2 6 $ & ( 6 $ 9 6 6 , ) 6 9 ' ' $ $ 9 6 6 9 6 6 9 6 6 9 / & ' h [ w 9 / & ' 2 8 7 9 / & ' 6 ( 1 6 ( 9 / & ' , 1 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 34 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver vss1 to vss3 can be connected to the same ground supply. the vlcd pins (vlcdout, vlcdsense , vlcdin) can be connected if v lcd is supplied from external. an external capacitor of 300 nf minimum is recommended for vlcd. for high display loads, 1 ? f is suggested. 8.10 lcd voltage 8.10.1 v lcd pins the pca8538 has 3 v lcd pins: vlcdin ? v lcd supply input vlcdout ? v lcd voltage output vlcdsense ? v lcd regulation circuitry input the v lcd voltage can be generated on-chip or externally supplied. internal v lcd generation: when the internal v lcd generation is selected (cpe = 1), the v lcd voltage is available on pin vlcdout. the pins vlcdin and vlcdsense must be connected to the pin vlcdout. external v lcd supply: when the external v lcd supply is selected (cpe = 0), the v lcd voltage must be supplied to the pin vlcdin. the pins vlcdout and vlcdsense should be connected together. 8.10.2 external v lcd supply v lcd can be directly supplied to the vlcdin pin. in this case, the in ternal charge pump must not be enabled, otherwise an extra current may occur on pin vdd2 and pin vlcd. when v lcd is supplied externally, no internal temperature compensation occurs on this voltage even if bit tce is set logic 1 (see section 8.10.4 ). the v lcd voltage which is supplied externally will be ava ilable at the segments and backplanes of the device through the chosen bias system. also programming th e v[8:0] bit field has no effect on the externally supplied v lcd . 8.10.3 internal v lcd generation v lcd can be generated by an on-chip char ge pump and controlled by command ( table 15 on page 14 ). the v lcd voltage is available on pin vlcdout. the charge pump is controlled by the charge-pump-ctrl command (see table 14 on page 14 ). it can be enabled with the cpe bit. the multiplier setting can be configured with the cpc[2:0] bits. the charge pump can generate a v lcd up to 5 ? v dd2 . 8.10.3.1 v lcd programming v lcd can be programmed by using the v[8:0] (see table 15 on page 14 ). the final value of v lcd is a combination of the programme d v[8:0] value and the output of the temperature compensation block, vt[8:0] (see equation 2 ). the system is exemplified in figure 14 . pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 35 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver in equation 2 the main parameters are the programmed digital value term and the compensated temperature term. (2) 1. v[8:0] is the binary value of the programmed voltage. 2. vt[8:0] is the binary value of the temper ature compensated voltage. its value comes from the temperature compensation block and is a two?s complement which has the value 0h at 20 ? c. 3. m and n are fixed values (see ta b l e 3 1 and figure 15 ). figure 15 shows how v lcd changes with the programmed value of v[8:0]. fig 14. v lcd generation including temperature compensation d d d 7 ( 0 3 ( 5 $ 7 8 5 ( 5 ( $ ' 2 8 7 7 ' > @ 9 > @ 9 / & ' q p 9 / & ' 7 ( 0 3 ( 5 $ 7 8 5 ( & 2 0 3 ( 1 6 $ 7 , 2 1 6 / $ 6 / % 6 / & 6 / ' 6 / ( 6 / ) 7 7 7 7 9 7 > @ table 31. parameters of v lcd generation symbol value unit m3.99v n0.03v v lcd v8 :0 ?? vt 8 :0 ?? + ?? n ? m + = pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 36 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver remarks: 1. it is important that v[8:0] is set to such a value that the resultant v lcd , including the temperature compensation vt[8:0], is higher than v dd2 . 2. programmable range of v[8:0] is from 0h to 1ffh. this would allow achieving a v lcd above 12 v but 12 v is the built-in automatic limit. 8.10.3.2 v lcd driving capability figure 16 illustrates the main factor determining how much curr ent the charge pump can deliver. the output resistance of the charge pump is specified in ta b l e 3 2 . (1) v[8:0] must be set so that v lcd > v dd2 . (2) automatic limitation for v lcd > 12 v. fig 15. v lcd programming of pca8538 (assuming vt[8:0] = 0h) d d d p 9 / & ' 9 > @ q 9 9 ' ' & k k k fig 16. charge pump model (used to characterize the driving strength) 7 k h r u h w l f d o 9 / & ' y d o x h 9 / & ' [ 9 ' ' r u 9 / & ' [ 9 ' ' r u 9 / & ' [ 9 ' ' r u 9 / & ' [ 9 ' ' 2 x w s x w 5 h v l v w d q f h 5 r 9 / & ' 2 8 7 5 h j x o d w h g g h v l u h g 9 / & ' 7 k l v v x s s o l h v w k h v h j p h q w v d q g e d f n s o d q h v d d d pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 37 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver remark: the pca8538 has a built-in automatic limitation of v lcd , set to 12 v. the maximum v lcd that can be programmed is expressed by the following equation: , where n is the mult iplication factor of the charge pump. i load is the overall current sink by the segments and backplanes outputs depending on the display, plus the on-chip v lcd current consumption. with these values, it can be calculated how much current the charge pump can drive under certain conditions, as shown in figure 17 and figure 18 . table 32. output resistance of the charge pump r ito(vss2) , r ito(vdd2) , r ito(vlcdout) =50 ? . charge pump configuration r o(vlcdout) (typical) unit v lcd =2 ? v dd2 2.5 k? v lcd =3 ? v dd2 6k ? v lcd =4 ? v dd2 10.5 k ? v lcd =5 ? v dd2 18 k ? conditions: v dd2 = 3.0 v, r ito(vss2) , r ito(vdd2) , r ito(vlcdout) =50 ? , t amb =27 ? c. charge pump configuration: (1) v lcd =2 ? v dd2 . (2) v lcd =3 ? v dd2 . (3) v lcd =4 ? v dd2 . (4) v lcd =5 ? v dd2 . i load is the overall current sink by the segment s and backplanes outputs depending on the display, plus the on-chip v lcd current consumption. reading example : v lcd can be programmed to 10 v by usi ng the charge pump configuration (3) or (4). with configuration (3), v lcd can be programmed to 10 v for a current load up to about 120 ? a. with configuration (4), v lcd can be programmed to 10 v for a current load up to about 260 ? a. remark: only the charge pump configurat ion (4) allows programming v lcd = 12 v when v dd2 =3.0v. fig 17. charge pump driving capability with v dd2 =3.0v v lcd max ?? min 12 v, nv dd2 r o vlcdout ?? i load ? ? ?? , o r d g ? $ d d d 9 / & ' 9 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 38 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver conditions: v dd2 = 5.0 v, r ito(vss2) , r ito(vdd2) , r ito(vlcdout) =50 ? , t amb =27 ? c. charge pump configuration: (1) v lcd =2 ? v dd2 . (2) v lcd =3 ? v dd2 . (3) v lcd =4 ? v dd2 . (4) v lcd =5 ? v dd2 . i load is the overall current sink by the segment and backplane outputs depending on the display, plus the on-chip v lcd current consumption. reading example : v lcd can be programmed to 10 v by usi ng the charge pump configuration (2) or (3). with configuration (2), v lcd can be programmed to 10 v for a current load up to about 780 ? a. with configuration (3), v lcd can be programmed to 10 v for a current load up to about 940 ? a. remark: the charge pump configuration (4) has no benef it compared to configuration (3) and is therefore not recommended when v dd2 =5.0v. fig 18. charge pump driving capability with v dd2 =5.0v , o r d g ? $ d d d 9 / & ' 9 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 39 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver it has to be considered that the driving capabi lity of the charge pump is depending on the resistance of the indium tin oxide (ito) tracks, see figure 20 and figure 19 . conditions: v dd2 = 3 v; charge pump configuration: v lcd =4 ? v dd2 ; v lcd =8v; t amb =27 ? c. (1) r ito(vss2) , r ito(vdd2) , r ito(vlcdout) =50 ? . (2) r ito(vss2) , r ito(vdd2) , r ito(vlcdout) =100 ? . i load is the overall current sink of the segment and backplane outputs depending on the display, plus the on-chip v lcd current consumption. fig 19. v lcd with respect to i load at v dd2 =3v conditions: v dd2 = 5 v; charge pump configuration: v lcd =2 ? v dd2 ; v lcd =8v; t amb =27 ? c. (1) r ito(vss2) , r ito(vdd2) , r ito(vlcdout) =50 ? . (2) r ito(vss2) , r ito(vdd2) , r ito(vlcdout) =100 ? . i load is the overall current sink of the segment and backplane outputs depending on the display, plus the on-chip v lcd current consumption. fig 20. v lcd with respect to i load at v dd2 =5v , o r d g ? $ d d d 9 / & ' 9 , o r d g ? $ d d d 9 / & ' 9 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 40 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.4 temperature measurement and temperature compensation of v lcd 8.10.4.1 temperature readout the pca8538 has a built-in temperature sensor which provides an 8-bit digital value (td[7:0]) of the ambient temperature. this value can be read by command (see section 8.2.6 on page 12 and section 8.2.7 on page 12 ). the actual temperature is determined from td[7:0] using equation 3 . (3) td[7:0] = ffh means that no temperature readout is available or was performed. ffh is the default value after power-on reset (por). the measurement needs about 8 ms to complete. it is repeated periodically every second as long as bit tme is set logic 1 (see table 17 on page 16 ). due to the nature of a temperature sensor, oscillations ma y occur. to avoid this, a filter has been implemented in pca8538. a control bit, tmf, is implemented to enable or disable the digital temperature filter (see table 17 on page 16 ). the system is exemplified in figure 21 . the digital temperature filter introduces a certain delay in the measurement of the temperature. th is behavior is illustrated in figure 22 . fig 21. temperature measurement block with digital temperature filter t ? c ?? 0.6275 td 7 : 0 ?? 40 ? ? = 7 ( 0 3 ( 5 $ 7 8 5 ( 0 ( $ 6 8 5 ( 0 ( 1 7 % / 2 & . ' , * , 7 $ / 7 ( 0 3 ( 5 $ 7 8 5 ( ) , / 7 ( 5 7 ' > @ x q i l o w h u h g 7 ' > @ i l o w h u h g h q d e o h g r u g l v d e o h g e \ e l w 7 0 ) 7 r w k h u h d g r x w u h j l v w h u d q g w r w k h 9 / & ' f r p s h q v d w l r q e o r f n d d d pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 41 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.4.2 temperature adjustment of the v lcd due to the temperature dependency of the liquid crystal viscosity, the lcd supply voltage may have to be adjusted at different temperatures to maintain optimal contrast. the temperature characteristics of the liquid is provided by the lcd manufacturer. the slope has to be set to compensate for the liquid behavior. internal temperature compensation can be enabled via bit tce (see table 17 on page 16 ). the ambient temperature range is split up to six programmable regions and to each a different temperature coefficient can be applied (see figure 23 ). (1) environment temperature, t1 ( ? c). (2) measured temperature, t2 ( ? c). (3) temperature deviation, ? t=t2 ? t1. fig 22. temperature measurement delay w v d d d 7 ? & 7 p h d v ? & pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 42 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver the temperature regions are determined by programming the temperature limits t1 to t4 via the tc-set-1 to tc -set-4 commands (see section 8.4.2 on page 17 ). the temperature coefficients can be selected from a choice of eight different slopes. each one of theses coefficients is independently select ed via the tc-slope command (see section 8.4.3 on page 18 ). [1] the relation between the actual temp erature and td[7:0] is derived from equation 3 on page 40 . remark: the programming has to be made such that t1 < t2 and t3 < t4 otherwise the v lcd temperature compensati on will not be executed. fig 23. example of segmented temperature coefficients table 33. temperature regions t1t[2:0] to t4t[2:0] temperature region 1 and 2 temperature region 3 and 4 t1, t2 ( ?c) corresponding td value [1] t3, t4 ( ?c) corresponding td value [1] 000 ? 34 10 +29 110 001 ? 27 20 +38 124 010 ? 21 30 +47 138 011 ? 15 40 +55 152 100 ? 950+64166 101 ? 260+73180 110 +4 70 +82 194 111 +10 80 +91 208 ? & 6 $ 6 % 6 & 6 ' 6 ( 6 ) $ % & ' ( ) 7 7 ? & 7 7 ] h u r r i i v h w d d d ? & pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 43 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] the relationship between the temperature coefficients sa to sf and the slope factor is derived from the following equation: , where lsb of v[8:0] ? 30 mv. [2] default value. the binary value of the temperature compensated voltage vt[8:0] is calculated according to table 35 . 8.10.5 lcd voltage selector the lcd voltage selector co-ordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the set-bias-mode command (see table 16 on page 15 ) and the set-mux-mode command (see table 20 on page 19 ). table 34. temperature coefficients tsa[2:0] to tsf[2:0] value slope factor (mv/ ?c) temperature coefficients sa to sf [1] 000 [2] 00 . 0 0 0 001 ? 6 ? 0.125 010 ? 12 ? 0.250 011 ? 24 ? 0.500 100 ? 60 ? 1.250 101 +6 +0.125 110 +12 +0.250 111 +24 +0.500 table 35. calculation of the temperature compensated value vt temperature (?c) digital temperature: td[7:0] binary value of the temperature compensated voltage: vt[8:0] sn 0.6275 ? c ?? lsb of v[8:0] mv ?? ------------------------------------------------ slope factor (mv/ ? c ? ? = t40 ? c ? ? td 7:0 ?? 0 = 96 t2 ? ?? ? sc t2 t1 ? ?? sb t1 sa ? ? ? ? ? 40 ? c ? tt1 ?? 0td 7:0 ?? t1 ? ? 96 t2 ? ?? ? sc t2 t1 ? ?? sb t1 td 7:0 ?? ? ?? sa ? ? ? ? ? t1 t t2 ?? t1 td 7:0 ?? t2 ? ? 96 t2 ? ?? ? sc t2 td 7:0 ?? ? ?? sb ? ? ? t2 t 20 ? c ?? t2 td 7:0 ?? 96 ? ? 96 td 7:0 ?? ? ?? ? sc ? 20 ? ctt3 ?? 96 td 7:0 ?? t3 ? ? td 7:0 ?? 96 ? ?? sd ? t3 t t4 ?? t3 td 7:0 ?? t4 ? ? t3 96 ? ?? sd ? td 7:0 ?? t3 ? ?? se ? + t4 t 105 ? c ?? t4 td 7:0 ?? 231 ? ? t3 96 ? ?? sd t4 t3 ? ?? se td 7 :0 ?? t4 ? ?? sf ? + ? + ? pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 44 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] determined from equation 6 . [2] determined from equation 5 . [3] in these examples, the discrimination fa ctor and hence the contrast ratios are smaller. the advantage of these lcd drive mod es is a power saving from a reduction of v lcd . intermediate lcd biasing voltages are obtained from an internal voltage divider. the biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of v lcd and the resulting discrimination ratios (d), are given in table 36 . discrimination is a term which is defined as the ratio of the on and off rms voltage across a segment. it can be tho ught of as a measurement of contrast. a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th(off) ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode, a suitable choice is v lcd >3v th(off) . bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias a = 3 for 1 4 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 4 : (4) where v lcd is the resultant voltage at the lcd segment and where the values for n are table 36. lcd drive modes: summary of characteristics lcd drive mode number of: lcd bias configuration [1] v lcd [2] backplanes levels static 1 2 static 0 1 ? v on(rms) 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 2.828 ? v off(rms) 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 3.0 ? v off(rms) 1:2 multiplex [3] 25 1 4 0.395 0.729 1.845 2.529 ? v off(rms) 1:4 multiplex [3] 43 1 2 0.433 0.661 1.527 2.309 ? v off(rms) 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 3.0 ? v off(rms) 1:4 multiplex 4 5 1 4 0.331 0.545 1.646 3.024 ? v off(rms) 1:6 multiplex [3] 63 1 2 0.456 0.612 1.341 2.191 ? v off(rms) 1:6 multiplex 6 4 1 3 0.333 0.509 1.527 3.0 ? v off(rms) 1:6 multiplex 6 5 1 4 0.306 0.467 1.527 3.266 ? v off(rms) 1:8 multiplex [3] 83 1 2 0.467 0.586 1.254 2.138 ? v off(rms) 1:8 multiplex 8 4 1 3 0.333 0.471 1.414 3.0 ? v off(rms) 1:8 multiplex 8 5 1 4 0.293 0.424 1.447 3.411 ? v off(rms) 1:9 multiplex [3] 93 1 2 0.471 0.577 1.225 2.121 ? v off(rms) 1:9 multiplex 9 4 1 3 0.333 0.454 1.374 3.000 ? v off(rms) 1:9 multiplex 9 5 1 4 0.289 0.408 1.414 3.464 ? v off(rms) v off rms ?? v lcd ---------------------- - v on rms ?? v lcd ---------------------- d v on rms ?? v off rms ?? ---------------------- - = 1 1a + ------------ - v on rms ?? a 2 2a n ++ n 1a + ?? ? ----------------------------- - v lcd = pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 45 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver n = 1 for static mode n = 2 for 1:2 multiplex n = 4 for 1:4 multiplex n = 6 for 1:6 multiplex n = 8 for 1:8 multiplex n = 9 for 1:9 multiplex the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 5 : (5) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 6 : (6) v lcd is sometimes referred as the lcd operating voltage. 8.10.5.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependent on the lcd liquid used. the rms voltage, at which a pixel is switched on or off, determine the transmissibility of the pixel. for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v th(off) ) and the other at 90 % relative transmission (at v th(on) ), see figure 24 . for a good contrast performance, the following rules should be followed: (7) (8) v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a, n (see equation 4 to equation 6 ) and the v lcd voltage. v th(off) and v th(on) are properties of the lcd liquid and can be provided by the module manufacturer. v th(off) is sometimes named v th . v th(on) is sometimes named saturation voltage v sat . it is important to match the module properties to those of the driver in order to achieve optimum performance. v off rms ?? a 2 2a ? n + n 1a + ?? ? ----------------------------- - v lcd = d v on rms ?? off rms ?? ---------------------- - a 2 2a n ++ a 2 2a ? n + --------------------------- == v on rms ?? v th on ?? ? v off rms ?? v th off ?? ? pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 46 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver fig 24. electro-optical characteristic: relative transmission curve of the liquid 9 5 0 6 > 9 @ 2 ) ) 6 ( * 0 ( 1 7 * 5 ( < 6 ( * 0 ( 1 7 2 1 6 ( * 0 ( 1 7 9 w k r i i 9 w k r q 5 h o d w l y h 7 u d q v p l v v l r q d d d pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 47 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.6 lcd drive mode waveforms 8.10.6.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v on(rms) (t) = v lcd . v off(rms) (t) = 0 v. fig 25. static drive mode waveform s, line inversion mode (n = 1) d d d 9 6 6 9 / & ' 9 6 6 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' v w d w h 9 % 3 6 q 6 q v w d w h 9 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h r q v w d w h r i i 7 i u pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 48 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.6.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pca8538 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 26 and figure 27 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.791v lcd . v off(rms) (t) = 0.354v lcd . fig 26. waveforms for the 1:2 multiplex drive mode, 1 2 bias, line inversion mode (n = 1) d d d v w d w h % 3 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h 9 6 6 9 / & ' 9 / & ' 9 6 6 9 6 6 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 6 q 6 q 7 i u pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 49 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.745v lcd . v off(rms) (t) = 0.333v lcd . fig 27. waveforms for the 1:2 multiplex drive mode, 1 3 bias, line inversion mode (n = 1) d d d v w d w h % 3 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 50 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.6.3 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 28 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.577v lcd . v off(rms) (t) = 0.333v lcd . fig 28. waveforms for the 1:4 multiplex drive mode, 1 3 bias, line inversion mode (n = 1) d d d v w d w h % 3 e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h % 3 d : d y h i r u p v d w g u l y h u % 3 6 q 6 q 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 51 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.6.4 1:6 multiplex drive mode when six backplanes are provided in the lcd, the 1:6 multiplex driv e mode applies. the pca8538 allows the use of 1 3 bias or 1 4 bias in this mode as shown in figure 29 and figure 30 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.509v lcd . v off(rms) (t) = 0.333v lcd . fig 29. waveforms for 1:6 multiplex drive mode, 1 3 bias, line inversion mode (n = 1) d d d v w d w h v w d w h / & ' v h j p h q w v 7 i u 9 / & ' % 3 9 / & ' 9 / & ' 9 6 6 9 / & ' % 3 9 / & ' 9 / & ' 9 6 6 9 / & ' % 3 9 / & ' 9 / & ' 9 6 6 9 / & ' % 3 9 / & ' 9 / & ' 9 6 6 9 / & ' % 3 9 / & ' 9 / & ' 9 6 6 9 / & ' % 3 9 / & ' 9 / & ' 9 6 6 9 / & ' 6 q d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w 9 / & ' 9 / & ' 9 6 6 9 / & ' 6 q 9 / & ' 9 / & ' 9 6 6 9 / & ' v w d w h 9 / & ' 9 / & ' 9 6 6 9 / & ' v w d w h 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 52 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.467v lcd . v off(rms) (t) = 0.306v lcd . fig 30. waveforms for 1:6 multiplex drive mode, 1 4 bias, line inversion mode (n = 1) d d d v w d w h v w d w h 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 6 6 v w d w h 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 v w d w h 6 q 6 q 7 i u d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 53 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.6.5 1:8 multiplex drive mode v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.424v lcd . v off(rms) (t) = 0.293v lcd . fig 31. waveforms for 1:8 multiplex drive mode, 1 4 bias, line inversion mode (n = 1) d d d % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 6 q 6 q v w d w h v w d w h 9 / & ' 9 / & ' v w d w h v w d w h 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 7 i u d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 54 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.10.6.6 1:9 multiplex drive mode v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.408v lcd . v off(rms) (t) = 0.289v lcd . fig 32. waveforms for 1:9 multiplex drive mode with 1 4 bias and line inversion mode (n = 1) d d d 9 / & ' % 3 % 3 % 3 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 6 q 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 6 6 6 q 9 / & ' 9 / & ' 9 6 6 v w d w h v w d w h 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 6 6 v w d w h / & ' v h j p h q w v v w d w h pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 55 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.408v lcd . v off(rms) (t) = 0.289v lcd . fig 33. waveforms for 1:9 multiplex drive mode with 1 4 bias and frame inversion mode 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' % 3 % 3 6 q 6 q v w d w h v w d w h 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 % 3 v w d w h v w d w h / & ' v h j p h q w v 7 i u 7 i u i u d p h q i u d p h q d d d pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 56 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.11 backplane outputs the lcd drive section includes nine backplane outputs: com0 to com8. the backplanes are double implemented to offer a higher flexibilit y for the glass layout. the backplane output signals are generated based on the selected lcd multiplex drive mode. table 37 describes which outputs are active for each of the multiplex drive modes and what signal is generated. ta b l e 3 8 describes the corresponding layout topology. 8.11.1 driving strength on the backplanes corresponding output pins (comx), which are carrying the same signal (bpn), may optionally be connected to the display. this a llows gaining a higher dr iving strength. if not required, the unused pins can be left open-circuit. table 37. mapping of output pins and corresponding output signals with respect to the multiplex driving mode multiplex drive mode output pin com0 com1 com2 com3 com4 com5 com6 com7 com8 signal static bp0 bp0 bp0 bp0 bp0 bp0 bp0 bp0 bp0 1:2 bp0 bp1 bp0 bp1 bp0 bp1 bp0 bp1 bp0 1:4 bp0 bp1 bp2 bp3 bp0 bp3 bp2 bp1 bp0 1:6 bp0 bp1 bp2 bp3 bp4 bp5 bp2 bp1 bp0 1:8 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 bp0 1:9 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 bp8 table 38. layout topology of output pins and correspondi ng output signals with respect to the multiplex driving mode multiplex drive mode static 1:2 1:4 1:6 1:8 1:9 signal on pin signal on pin signal on pin signal on pin signal on pin signal on pin bp0 com0 bp0 com0 bp0 com0 bp0 com0 bp0 com0 bp0 com0 com1 com2 com4 co m8 com8 bp1 com1 com2 com4 com8 bp1 c om1 bp1 com1 bp2 com2 com3 com6 bp1 com1 c om7 bp2 com2 bp3 com3 com4 com8 com7 bp2 c om2 bp3 com3 bp4 com4 com5 bp1 com1 bp2 com2 com6 bp4 com4 bp5 com5 com6 com3 com6 bp3 c om3 bp5 com5 bp6 com6 com7 com5 bp3 com3 bp4 com4 bp6 com6 bp7 com7 com8 com7 com5 bp5 c om5 bp7 com7 bp8 com8 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 57 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.12 segment outputs the lcd drive section includes 102 segment outputs (s0 to s101) which must be connected directly to the lcd. the segment output signals are generated based on the multiplexed backpla ne signals and with data resident in the display register. when less than 102 segment outputs are required, the unused segment outputs must be left open-circuit. 8.13 display register the display register holds the display data while the corresponding multiplex signals are generated. 8.14 display ram the display ram is a static 102 ? 9-bit ram which stores lcd data. logic 1 in the ram bit map indicates the on-state, logic 0 the off-state of the corresponding lcd element. there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements ? the ram columns and the segment outputs ? the ram rows and the backplane outputs. the display ram bit map, figure 34 on page 62 , shows row 0 to row 8 which correspond with the backplane outputs com0 to com8, and column 0 to column 101 which correspond with the segment outputs s0 to s101. in multiplexed lcd applications, the data of each row of the display ram is time-multiplexed with the corresponding backplane (row 0 with com0, row 1 with com1, and so on). when display data is transmitted to the pca8538, the display bytes received are stored in the display ram in accordance with the select ed lcd multiplex drive mode. the data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. depending on the current multiplex drive mode, data is stored singularly, in pairs, quadruples, sextuples or bytes. 8.14.1 data pointer the addressing mechanism for the display ram is realized using a data pointer. this allows the loading of an individual display data byte, or a series of display data bytes into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the data-pointer-x and data-pointer-y commands. following these commands, an arriving data byte is stored starting at the display ram address indicated by the data pointer. the data pointer is automatically increm ented in accordance with the chosen lcd multiplex drive mode configuration. after each byte is stored, the contents of the data pointer are incremented pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 58 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver ? by eight (static drive mode) ? by four (1:2 multiplex drive mode) ? by two (1:4 multiplex drive mode) ? by one or two (1:6 multiplex drive mode) ? by one (1:8 and 1:9 multiplex drive mode) when the address counter reaches the end of th e ram, it stops incrementing after the last byte is transmitted. redundant bits of the la st byte and subsequent bytes transmitted are discarded. to send new ram data, the data pointer must be reset. if a data access with the i 2 c- or spi-bus is terminated early, then the state of the data pointer is unknown. the data pointer must then be re-written before further ram accesses. 8.14.1.1 data pointer in cascade configuration in cascaded applications each pca8538 in the cascade must be addressed separately. initially, the first pca8538 is selected by sending the device-address command matching the first hardware address. then the data po inter is set to the preferred display ram address with the data-pointer-x and data-pointer-y commands. storage is allowed only when the content of the device address register matches with the hardware device address applied to a0 and a1 (see section 8.2.3 ). if the content of the device address register and the hardware devi ce address do not match, then data storage is inhibited but the data pointer is increm ented as if data storage had taken place. 8.14.2 ram filling for the following examples showing the ram filling patterns, it is assumed that the bits shown in ta b l e 3 9 are transferred to the ram. table 39. bit scheme used to illu strate the ram filling patterns bit 7 6 5 4 3 2 1 0 byte msb lsb 1 aa7 aa6 aa5 aa4 aa3 aa2 aa1 aa0 2 ab7 ab6 ab5 ab4 ab3 ab2 ab1 ab0 : : ::::::: 204 hk7 hk6 hk5 hk4 hk3 hk2 hk1 hk0 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 59 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.14.2.1 ram filling in static drive mode in the static drive mode the eight transmitte d data bits are placed in eight successive display ram columns in row 0 (see ta b l e 4 0 ). in order to fill the whole ram row, 13 bytes mu st be sent to the pca8538. any data bits that spill over the ram and addition al data bytes se nt are discarded. 8.14.2.2 ram filling in 1:2 multiplex drive mode in the 1:2 multiplex drive mode the eight tr ansmitted data bits are placed in four successive display ram columns of two rows (see ta b l e 4 1 ). in order to fill the whole two ram rows 26 bytes need to be sent to the pca8538. any data bits that spill over the ram and ad ditional data bytes sent are discarded. table 40. ram filling in static drive mode ram row/ backplane output (com) ram column/segment output (s) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 : 99 100 101 0 aa7 aa6 aa5 aa4 aa3 aa2 aa1 aa0 ab7 ab6 ab5 ab4 ab3 ab2 ab1 ab0 : am4 am3 am2 1 ----------------:- - - : :::::::::::::::::: : : 8 ----------------:- - - table 41. ram filling in 1:2 multiplex drive mode ram row/ backplane output (com) ram column/segment output (s) 0 1 2 3 4 5 6 7 : 99 100 101 0 aa7 aa5 aa3 aa1 ab7 ab5 ab3 ab1 : ay1 az7 az5 1 aa6 aa4 aa2 aa0 ab6 ab4 ab2 ab0 : ay0 az6 az4 2 --------:--- : :::::::::::: 8 --------:--- pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 60 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.14.2.3 ram filling in 1:4 multiplex drive mode in the 1:4 multiplex drive mode the eight transmitted data bits are placed in two successive display ram colu mns of four rows (see ta b l e 4 2 ). in order to fill the whole fo ur ram rows 51 bytes need to be sent to the pca8538. depending on the start address of the data pointer, there is the possibility for a boundary condition. this occurs when more data bits are sent than fit into the remaining ram. the additional data bits are discarded. 8.14.2.4 ram filling in 1:6 multiplex drive mode in the 1:6 multiplex drive mode the eight transmitted data bits are placed as shown in ta b l e 4 3 . the remaining bits of a byte are wrapped up into the next colu mn. in order to fill the whole ram addresses 77 bytes need to be sent to the pca8 538. any data bits that spill over the ram and additional data bytes sent are discarded. table 42. ram filling in 1:4 multiplex drive mode ram row/ backplane output (com) ram column/segment output (s) 0 1 2 3 : 99 100 101 0 aa7 aa3 ab7 ab3 : bx3 by7 by3 1 aa6 aa2 ab6 ab2 : bx2 by6 by2 2 aa5 aa1 ab5 ab1 : bx1 by5 by1 3 aa4 aa0 ab4 ab0 bx0 by4 by0 4 ----:--- : :::::::: 8 ----:--- table 43. ram filling in 1:6 multiplex drive mode ram row/ backplane output (com) ram column/segment output (s) 0 1 2 3 : 99 100 101 0 aa7 aa1 ab3 ac5 : cw5 cx7 cx1 1 aa6 aa0 ab2 ac4 : cw4 cx6 cx0 2 aa5 ab7 ab1 ac3 : cw3 cx5 cy7 3 aa4 ab6 ab0 ac2 : cw2 cx4 cy6 4 aa3 ab5 ac7 ac1 : cw1 cx3 cy5 5 aa2 ab4 ac6 ac0 : cw0 cx2 cy4 6 ----:--- 7 ----:--- 8 ----:--- pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 61 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.14.2.5 ram filling in 1:8 multiplex drive mode in the 1:8 multiplex drive mode the eight transmi tted data bits are placed into eight rows of one display ram column (see ta b l e 4 4 ). in order to fill the whole ra m addresses 102 bytes need to be sent to the pca8538. additional data bytes sent are discarded. 8.14.2.6 ram filling in 1:9 multiplex drive mode in the 1:9 multiplex drive mode the transmitte d bytes are stored continuously in the eight ram rows until ram column 101 while the da ta pointer x is au tomatically wrapped around from ram column 0 to ram column 101 (data pointer y remains logic 0). then the data pointer x wraps around to ram column 0 while data pointe r y is set to logic 1 to fill ram row 8. from the next bytes sent, only th e lsb (bit 0) is stored in ram row 8. the 7 most significant data bits are discarded. in order to fill the w hole ram addresses 204 bytes need to be sent to the pca8538 but an y data bits that spill over the ram and additional data bytes sent are discarded. table 44. ram filling in 1:8 multiplex drive mode ram row/ backplane output (com) ram column/segment output (s) 0 1 2 : 99 100 101 0 aa7 ab7 ac7 : dv7 dw7 dx7 1 aa6 ab6 ac6 : dv6 dw6 dx6 2 aa5 ab5 ac5 : dv5 dw5 dx5 3 aa4 ab4 ac4 : dv4 dw4 dx4 4 aa3 ab3 ac3 : dv3 dw3 dx3 5 aa2 ab2 ac2 : dv2 dw2 dx2 6 aa1 ab1 ac1 : dv1 dw1 dx1 7 aa0 ab0 ac0 : dv0 dw0 dx0 8 ---:--- table 45. ram filling in 1:9 multiplex drive mode ram row/ backplane output (com) ram column/segment output (s) 0 1 2 : 99 100 101 0 aa7 ab7 ac7 : dv7 dw7 dx7 1 aa6 ab6 ac6 : dv6 dw6 dx6 2 aa5 ab5 ac5 : dv5 dw5 dx5 3 aa4 ab4 ac4 : dv4 dw4 dx4 4 aa3 ab3 ac3 : dv3 dw3 dx3 5 aa2 ab2 ac2 : dv2 dw2 dx2 6 aa1 ab1 ac1 : dv1 dw1 dx1 7 aa0 ab0 ac0 : dv0 dw0 dx0 8 dy0 dz0 ea0 : hi0 hj0 hk0 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 62 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.14.3 bank selection the pca8538 includes a ram bank switching feature in the static, 1:2, and 1:4 multiplex drive modes. a bank can be thought of as a collection of ram rows. the ram bank switching gives the provision for preparing di splay information in an alternative bank and to be able to switch to it once it is complete. figure 34 shows the location of the banks relative to the ram map. the display ram bitmap shows the direct relationship between the display ram column and the segment outputs, between the bits in a ram row and the backplane outputs, and between the ram rows and banks. fig 34. display ram bitmap and bank definition e d q n e d q n e d q n e d q n e d q n e d q n e d q n e d q n u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v & 2 0 f r o x p q v g l v s o d \ 5 $ 0 f r o x p q v v h j p h q w v r x w s x w v 6 v w d w l f g u l y h p r g h e d q n e d q n e d q n e d q n u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v & 2 0 f r o x p q v g l v s o d \ 5 $ 0 f r o x p q v v h j p h q w v r x w s x w v 6 p x o w l s o h [ g u l y h p r g h d d d e d q n e d q n u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v & 2 0 f r o x p q v g l v s o d \ 5 $ 0 f r o x p q v v h j p h q w v r x w s x w v 6 p x o w l s o h [ g u l y h p r g h pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 63 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver input and output banks can be set independently from one another with the bank-select commands (see section 8.7.2 on page 23 ). figure 35 shows the concept. in figure 36 an example is shown for the 1:4 multiplex drive mode where the displayed data is read from the first fo ur rows of the memory (bank 0) , while the transmitted data is stored in the second four rows of the me mory (bank 4). theses second four rows are currently not accessed for reading. therefore different content can be loaded into the first and second four ram rows. when switching to reading with the output-bank-select command it will be immediat ely displayed on the lcd. fig 35. example of bank sele ction in 1:4 multiplex mode fig 36. example of the input-bank-select an d the output-bank-se lect command with multiplex drive mode 1:4 % $ 1 . 0 , & 5 2 & 2 1 7 5 2 / / ( 5 ' , 6 3 / $ < % $ 1 . 5 $ 0 l q s x w e d q n v h o h f w f r p p d q g f r q w u r o v w k h l q s x w g d w d s d w k r x w s x w e d q n v h o h f w f r p p d q g f r q w u r o v w k h r x w s x w g d w d s d w k d d d d d d u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v & 2 0 f r o x p q v g l v s o d \ 5 $ 0 f r o x p q v v h j p h q w v r x w s x w v 6 r x w s x w 5 $ 0 e d q n w r w k h / & ' w r w k h 5 $ 0 l q s x w 5 $ 0 e d q n pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 64 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 8.14.3.1 input-bank-select the input-bank-select command (see table 26 on page 23 ) loads display data into the display ram in accordance with the selected lcd drive configuration (see figure 34 on page 62 ). ? in static drive mode, an individual content can be stored in each ram bank (bank 0 to bank 7 which corresponds to row 0 to row 7). ? in 1:2 multiplex drive mode, individual content for ram bank 0 (row 0 and row 1), ram bank 2 (row 2 and row 3), ram bank 4 (row 4 and 5) and ram bank 6 (row 6 and row 7) can be stored. ? in 1:4 multiplex drive mode individual conten t can be stored in ram bank 0 (row 0 to row 3) and ram bank 4 (row 4 to row 7). the input-bank-select command works inde pendently to the ou tput-bank-select command. 8.14.3.2 output-bank-select the output-bank-select command (see table 27 on page 24 ) selects the display ram transferring it to the display register in accordance with the selected lcd drive configuration (see figure 34 on page 62 ). ? in the static drive mode, it is possible to request the content of ram bank 1 (row 1) to ram bank 7 (row 7) for display instead of the default ram bank 0 (row 0). ? in 1:2 multiplex drive mode, the content of ram bank 2 (row 2 and row 3) or of ram bank 4 (row 4 and row 5) or of ram bank 6 (row 6 and row 7) may be selected instead of the default ram bank 0 (row 0 and row 1). ? in 1:4 multiplex drive mode, the content of ram bank 4 (row 4, 5, 6, and 7) may be selected instead of ram bank 0 (row 0, 1, 2, and 3). the output-bank-select command works in dependently to the input-bank-select command. pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 65 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 9. bus interfaces 9.1 control byte and register selection after initiating the communication over the bus and sending the slave address (i 2 c-bus, see section 9.2 ) or subaddress (spi-bus, see section 9.3 on page 70 ), a control byte follows. the purpose of this byte is to indicate both, the content for the following data bytes (ram or command) and to indica te that more control bytes will follow. typical sequences could be: ? slave address/subaddress - control byte - command byte - command byte - command byte - end ? slave address/subaddress - control byte - ram byte - ram byte - ram byte - end ? slave address/subaddress - control byte - command byte - control byte - ram byte - end this allows sending a mixture of ram and command data in one access or alternatively, to send just one type of data in one access. in this way, it is possible to configure the device and then fill the display ram with little overhead. the display bytes are stored in the display ram at the address specified by the data pointer. table 46. control byte description bit symbol value description 7co continue bit 0 last control byte 1 control bytes continue 6 to 5 rs[1:0] register selection 00, 10 command register 01 ram data 11 unused 4 to 0 - - unused fig 37. control byte format d d d q r w u h o h y d q w & 2 5 6 > @ 0 6 % / 6 % pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 66 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 9.2 i 2 c interface the i 2 c-bus is selected by connecting pin ifs to v dd1 . the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. in chip-on-glass (cog) app lications, where the track resistance between the sda output pin to the system sda input line can be significant, the bus pull-up resistor and the indium tin oxide (ito) track resistance may generate a voltage divider. as a consequence it may be possible that the ackn owledge cycle, generated by the lcd driver, cannot be interpreted as logic 0 by the ma ster. therefore it is an advantage for cog applications to have the acknowledge output separated from the data line. for that reason, the sda line of the pca8538 is split into sdi/sdain and sdaout. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sdaout pin to the system sdi/sdain line to guarantee a valid low level. by splitting the sda line into sdi/sdai n and sdaout (having the sdaout open circuit), the device could be used in a mode that ignores the acknowledge cycle. separating the acknowledge output from the serial data line can avoid design efforts to generate a valid ackno wledge level. however, in that case the i 2 c-bus master has to be set up in such a way that it ignores the acknowledge cycle. 2 by connecting pin sdaout to pin sdi/sda in the sdi/sdain line becomes fully i 2 c-bus compatible. the following definition assu mes sdi/sdain and sdaout are connected and refers to the pair as sda. 9.2.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time are interpreted as a control signal (see figure 38 ). 9.2.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low change of the data line, while the clock is high is defined as the start condition (s). 2. for further information, consider the nxp application note: ref. 1 ? an10170 ? . fig 38. i 2 c-bus - bit transfer 6 ' $ 6 & / d d d f k d q j h r i g d w d d o o r z h g g d w d o l q h v w d e o h g d w d y d o l g pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 67 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver a low-to-high change of the data line while th e clock is high is defined as the stop condition (p). the start and stop conditions are shown in figure 39 . 9.2.3 system configuration a device generating a message is a transmit ter; a device receiving a message is the receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves. the system configuration is shown in figure 40 . 9.2.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is un limited. each byte of 8 bits is followed by an acknowledge cycle. ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be considered). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 41 . fig 39. i 2 c-bus - definition of start and stop conditions 6 ' $ 6 & / 6 ' $ 6 & / d d d 6 6 7 $ 5 7 f r q g l w l r q 6 7 2 3 f r q g l w l r q fig 40. i 2 c-bus - system configuration d d d 6 ' $ 6 & / 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 6 / $ 9 ( 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 6 / $ 9 ( 5 ( & ( , 9 ( 5 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 68 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 9.2.5 i 2 c-bus controller the pca8538 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers. the only data output from pca8538 is the ackn owledge signals and the temperature readout byte of the selected device. 9.2.6 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 9.2.7 i 2 c-bus slave address device selection depends on the i 2 c-bus slave address. the least significant bit of the slave address byte is bit r/w (see ta b l e 4 8 ). bit 1 and bit 2 of the slave address are defined by connecting the inputs sa0 and sa1 to either v ss1 (logic 0) or v dd1 (logic 1). therefore, four instances of pca8538 can be distinguished on the same i 2 c-bus. fig 41. acknowledgement on the i 2 c-bus d d d 6 6 7 $ 5 7 f r q g l w l r q f o r f n s x o v h i r u d f n q r z o h g j h p h q w g d w d r x w s x w e \ w u d q v p l w w h u g d w d r x w s x w e \ u h f h l y h u 6 & / i u r p p d v w h u q r w d f n q r z o h g j h d f n q r z o h g j h table 47. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb slave address 0 1 1 1 0 sa1 sa0 r/w table 48. r/w -bit description r/w description 0 write data 1 read data pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 69 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 9.2.8 i 2 c-bus protocol the i 2 c-bus protocol is shown in figure 42 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the four pca8538 slave addresses available. all pca8538 with the corresponding sa1 and sa0 level acknowledge in parallel to the slave address, but all pca8538 with the alternative sa1 and sa0 levels ignore the whole i 2 c-bus transfer. after acknowledgement, a contro l byte follows which defines if the next byte is ram or command information. the control byte (see table 46 on page 65 ) also defines whether the next byte is a control byte or further ram or command data. for a temperature readout (see section 8.10.4.1 on page 40 ), the r/w bit must be logic 1. the next data byte following is provided by the pca8538 as shown in figure 43 . fig 42. i 2 c-bus protocol - write mode ( ; $ 0 3 / ( 6 d w u d q v p l w w z r e \ w h v r i 5 $ 0 g d w d d d d f r q w u r o e \ w h v o d y h d g g u h v v 5 $ 0 f r p p d q g e \ w h 5 : e w u d q v p l w w z r f r p p d q g e \ w h v f w u d q v p l w r q h f r p p d q g e \ w h d q g w z r 5 $ 0 g d w h e \ w h v 6 $ $ $ $ $ $ 3 & 2 0 0 $ 1 ' 5 $ 0 ' $ 7 $ 5 $ 0 ' $ 7 $ $ 6 $ 6 6 $ $ $ $ $ 3 & 2 0 0 $ 1 ' & 2 0 0 $ 1 ' $ 6 $ 6 6 $ $ $ $ 3 5 $ 0 ' $ 7 $ 5 $ 0 ' $ 7 $ $ 6 $ 6 6 $ $ 3 $ 6 $ 6 6 / % 6 0 % 6 5 6 5 & 2 fig 43. i 2 c-bus protocol - read mode d d d w h p s h u d w x u h u h d g r x w e \ w h v o d y h d g g u h v v 5 : 6 $ $ 6 $ 6 6 $ / % 3 6 0 % d f n q r z o h g j h i u r p 3 & $ d f n q r z o h g j h i u r p p d v w h u pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 70 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 9.3 spi interface the spi interface is selected by connecting pin ifs to v ss1 . data transfer to the device is made via a four-line spi-bus (see ta b l e 4 9 ). the spi-bus is initialized whenever the chip enable line pin ce is low. [1] the chip enable must not be wired permanently low. 9.3.1 data transmission the chip enable signal (ce ) is used to initialize data transmission. each data transfer is a byte, with the msb sent first. the first byte transmitted is the subaddress byte. the subaddress byte opens the communication with a read/write bit and a subaddress. the subaddress is used to identify multiple devices on one spi bus. figure 45 shows an example of an spi data transfer. table 49. serial interface symbol function description ce chip enable input; active low [1] when high, the interface is reset scl serial clock input input may be higher than v dd1 sdi/sdain serial data input input may be higher than v dd1 ; input data is sampled on the rising edge of scl sdo serial data output - fig 44. spi-bus protocol - data transfer overview table 50. subaddress byte definition bit symbol value description 7r/w data read or write selection 0 write data 1 read data 6to5 sa 01 subaddress ; other codes cause the device to ignore data transfer 4to0 - unused d d d g d w d e x v & ( 6 8 % $ ' ' 5 ( 6 6 ' $ 7 $ ' $ 7 $ ' $ 7 $ pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 71 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver for a temperature readout (see section 8.10.4.1 on page 40 ), the r/w bit must be logic 1. the next data byte following is provided by the pca8538 as shown in figure 46 . in this example, the bias system is set to 1 3 . the transfer is terminated by ce returning to logic 1. after the last bit is transmitted, the state of the sdi/sdain line is not important. fig 45. spi-bus example d d d 5 : 6 $ 6 & / 6 ' , & ( e e e e e e e e e e e e e e e e e e e e e e e e x q x v h g e l d v v \ v w h p % > @ & 2 5 6 x q x v h g fig 46. spi-bus protocol - read example data transfers are terminated by de-asserting ce (set ce to logic 1). fig 47. spi-bus protocol - write example v x e d g g u h v v 5 : w h p s h u d w x u h u h d g r x w e \ w h d d d ( ; $ 0 3 / ( 6 d w u d q v p l w w z r e \ w h v r i g l v s o d \ 5 $ 0 g d w d d d d f r q w u r o e \ w h v x e d g g u h v v 5 $ 0 f r p p d q g e \ w h 5 $ 0 ' $ 7 $ 0 6 % / 6 % 5 : e w u d q v p l w w z r f r p p d q g e \ w h v & 2 0 0 $ 1 ' f w u d q v p l w r q h f r p p d q g e \ w h d q g w z r g l v s o d \ 5 $ 0 g d w h e \ w h v & 2 5 6 5 6 5 $ 0 ' $ 7 $ 5 $ 0 ' $ 7 $ 5 $ 0 ' $ 7 $ & 2 0 0 $ 1 ' & 2 0 0 $ 1 ' pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 72 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 10. internal circuitry fig 48. device protection diagram d d d 9 / & ' 9 6 6 9 ' ' 9 6 6 9 6 6 9 6 6 9 6 6 9 ' ' 9 ' ' 9 ' ' 9 / & ' , 1 9 / & ' 6 ( 1 6 ( 9 / & ' 2 8 7 6 & / 6 ' , 6 ' $ , 1 6 ' $ 2 8 7 7 & 2 0 w r & 2 0 6 w r 6 6 < 1 & 6 < 1 & , ) 6 6 ' 2 & ( 6 $ 6 $ & / . 2 6 & $ $ 5 6 7 7 7 7 9 6 6 9 6 6 9 ' ' 9 6 6 9 6 6 9 6 6 9 ' ' 9 6 6 9 6 6 l q w r , & l q w r , & 7 7 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 73 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 11. safety notes caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. caution semiconductors are light sens itive. exposure to light s ources can cause the ic to malfunction. the ic must be protected agains t light. the protection must be applied to all sides of the ic. pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 74 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 12. limiting values [1] pass level; human body model (hbm), according to ref. 8 ? jesd22-a114 ? . [2] pass level; latch-up testing according to ref. 9 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [3] according to the store and transport requirements (see ref. 14 ? um10569 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. table 51. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd1 supply voltage 1 analog and digital ? 0.5 +6.5 v v dd2 supply voltage 2 charge pump ? 0.5 +6.5 v v dd3 supply voltage 3 analog ? 0.5 +6.5 v i dd1 supply current 1 analog and digital ? 50 +50 ma i dd2 supply current 2 charge pump ? 50 +50 ma i dd3 supply current 3 analog ? 50 +50 ma v lcd lcd supply voltage external supply, input on pin vlcdin ? 0.5 +20 v i dd(lcd) lcd supply current ? 50 +50 ma v i input voltage on pins clk, osc, a0, a1, rst , ifs, scl, sdi/sdain, sa0, ce , sa1, sync0, sync1 ? 0.5 +6.5 v on pin vlcdsense ? 0.5 +20 v i i input current ? 10 +10 ma v o output voltage on pins s0 to s101, com0 to com8, vlcdout ? 0.5 +20 v on pins sdo, sa0, sdaout, clk, sync0, sync1 ? 0.5 +6.5 v i o output current ? 10 +10 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p/out power dissipation per output -1 0 0m w v esd electrostatic discharge voltage hbm [1] - ? 2000 v i lu latch-up current [2] -1 5 0m a t stg storage temperature [3] ? 65 +150 ?c t amb ambient temperature operating device ? 40 +105 ?c pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 75 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 13. static characteristics table 52. static characteristics v dd1 , v dd2 , v dd3 = 2.5 v to 5.5 v; v ss1 = 0 v; v lcd = 4.0 v to 12.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd1 supply voltage 1 2.5 - 5.5 v v dd2 supply voltage 2 2.5 - 5.5 v v dd3 supply voltage 3 2.5 - 5.5 v v lcd lcd supply voltage v lcd ? v dd2 external supply, input on pin vlcdin 4.0 - 12.0 v internal supply, output on pin vlcdout 4.0 - 12.0 v i dd1 supply current 1 on pin vdd1 default condition after por and initialize command, see figure 49 -4 0 [1] 58 [2] ? a display enabled; internal clock -45 [1] - ? a i dd2 supply current 2 on pin vdd2 default condition after por and initialize command -0- ? a v dd2 =5v; charge pump at v lcd =2 ? v dd2 ; v lcd =8v; c vlcd = 100 nf; display disabled; see figure 50 -2 5- ? a i dd3 supply current 3 on pin vdd3 default condition after por and initialize command, see figure 51 -4 0 [3] 58 [4] ? a display enabled; internal clock -90 [3] - ? a i dd(lcd) lcd supply current on pin vlcdin; external v lcd =8v display disabled, see figure 52 -6 . 51 0 ? a mux 1:9; 1 4 bias; f fr = 80 hz; ram entirely filled with 1; frame inversion mode; display enabled; no display attached -85- ? a accuracy ? v lcd lcd voltage variation on pin vlcdout; internal v lcd ; v[8:0] = 86h; t amb =25 ?c; see figure 53 7950 8010 8070 mv pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 76 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver ? f fr frame frequency variation internal clock; ff[4:0] = 00111; t amb =25 ?c; see figure 54 77 80 83 hz ? t meas measurement temperature variation t amb =25 ?c; see figure 55 22 25 28 ?c output resistance r o(com[0:8]) output resistance on pin com0 to com8 external v lcd =8v - 1 - k ? r o(s[0:101]) output resistance on pin s0 to s101 external v lcd =8v - 2.5 - k ? logic on pins clk, osc, a0, a1, sync0, sync1, rst , ifs v i input voltage v ss1 ? 0.5 - v dd1 + 0.5 v v il low-level input voltage --0.3v dd1 v v ih high-level input voltage 0.7v dd1 --v i li input leakage current v i = v dd1 or v ss1 -0- ? a on pins clk, sync0, sync1 v o output voltage ? 0.5 - v dd1 + 0.5 v v oh high-level output voltage 0.8v dd1 --v v ol low-level output voltage --0.2v dd1 v i oh high-level output current output source current; v oh =4.6v; v dd1 =5v 1- - ma i ol low-level output current output sink current; v ol =0.4v; v dd1 =5v 1- - ma i lo output leakage current v o = v dd1 or v ss1 -0- ? a i 2 c-bus on pins scl, sdi/sdain v i input voltage v ss1 ? 0.5 - 5.5 v v il low-level input voltage --0.3v dd1 v v ih high-level input voltage 0.7v dd1 --v i li input leakage current v i = v dd1 or v ss1 -0- ? a table 52. static characteristics ?continued v dd1 , v dd2 , v dd3 = 2.5 v to 5.5 v; v ss1 = 0 v; v lcd = 4.0 v to 12.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 77 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] v dd1 =5v; t amb =25 ? c. [2] v dd1 = 5.5 v; t amb = 105 ? c. [3] v dd3 =5v; t amb =25 ? c. [4] v dd3 = 5.5 v; t amb = 105 ? c. on pin sdaout v o output voltage ? 0.5 - +5.5 v i ol low-level output current output sink current; v ol =0.4v 6- - ma i li input leakage current v i = v dd1 or v ss1 -0- ? a i lo output leakage current v o =v ss1 -0- ? a spi-bus on pins scl, sdi/sdain, ce v i input voltage on pins scl, sdi/sdain v ss1 ? 0.5 - 5.5 v on pin ce v ss1 ? 0.5 - v dd1 + 0.5 v v il low-level input voltage --0.3v dd1 v v ih high-level input voltage 0.7v dd1 --v i li input leakage current v i = v dd1 or v ss1 -0- ? a on pin sdo v o output voltage ? 0.5 - v dd1 + 0.5 v v oh high-level output voltage 0.8v dd1 --v v ol low-level output voltage --0.2v dd1 v i oh high-level output current output source current; v oh =4.6v; v dd1 =5v 1- - ma i ol low-level output current output sink current; v ol =0.4v; v dd1 =5v 1- - ma i lo output leakage current v o = v dd1 or v ss1 -0- ? a table 52. static characteristics ?continued v dd1 , v dd2 , v dd3 = 2.5 v to 5.5 v; v ss1 = 0 v; v lcd = 4.0 v to 12.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 78 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver default conditions after por and initialization. (1) v dd1 =5.5v. (2) v dd1 =5v. (3) v dd1 =3v. (4) v dd1 =2.5v. fig 49. typical i dd1 with respect to temperature (1) v dd2 = 3 v; charge pump at v lcd =3 ? v dd2 ; v lcd =8v; c vlcd = 100 nf; display disabled. (2) v dd2 = 5 v; charge pump at v lcd =2 ? v dd2 ; v lcd =8v; c vlcd = 100 nf; display disabled. fig 50. typical i dd2 with respect to temperature d d d 7 d p e ? & , ' ' ' ' , ' ' ? $ ? $ ? $ d d d 7 d p e ? & , ' ' ' ' , ' ' ? $ ? $ ? $ pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 79 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver default conditions after por. (1) v dd1 =5.5v. (2) v dd1 =5v. (3) v dd1 =3v. (4) v dd1 =2.5v. fig 51. typical i dd3 with respect to temperature conditions: external v lcd ; display disabled. fig 52. typical i dd(lcd) with respect to temperature d d d 7 d p e ? & , ' ' ' ' , ' ' ? $ ? $ ? $ d d d 7 d p e ? & , ' ' / & ' ' ' / & ' , ' ' / & ' ? $ ? $ ? $ 9 / & ' 9 / & ' 9 9 / & ' 9 9 / & ' 9 / & ' 9 9 / & ' 9 9 / & ' 9 / & ' 9 9 / & ' 9 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 80 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver conditions: v dd2 = 5 v; charge pump at v lcd =2 ? v dd2 ; v lcd = 8 v; v[8:0] = 134h; temperature compensation disabled. fig 53. typical v lcd variation with respect to temperature conditions: frame frequency presca ler = 00111; 80 hz typical. fig 54. typical frame frequency varia tion with respec t to temperature d d d 7 d p e ? & 9 / & ' / & ' 9 / & ' 9 9 9 d d d 7 d p e ? & i i u i u i i u + ] + ] + ] pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 81 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver fig 55. measurement temperature variation with respect to temperature d d d 7 d p e ? & 7 p h d v p h d v 7 p h d v ? & ? & ? & 7 p h d v p d [ p h d v p d [ 7 p h d v p d [ 7 p h d v w \ s p h d v w \ s 7 p h d v w \ s 7 p h d v p l q p h d v p l q 7 p h d v p l q pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 82 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 14. dynamic characteristics 14.1 general dynamic characteristics table 53. general dynamic characteristics v dd1 , v dd2 , v dd3 = 2.5 v to 5.5 v; v ss1 = 0 v; v lcd = 4.0 v to 12.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. all timing values are valid within the operating supply vo ltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss1 to v dd1 . symbol parameter conditions min typ max unit f clk(int) internal clock frequency on pin clk; ff[4:0] = 00111; t amb =25 ? c 11088 11520 11952 hz f clk(ext) external clock frequency on pin clk 6400 - 42700 hz t clk(h) high-level clock time external clock source used 5 - - ? s t clk(l) low-level clock time 5 - - ? s t wl(rst_n) rst_n low pulse width 3- - ? s c b capacitive load for each bus line i 2 c-bus - - 400 pf fig 56. driver timing waveforms d d d & / . w f o n + w f o n / i f o n 9 ' ' 9 ' ' pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 83 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 14.2 i 2 c-bus timing characteristics [1] t vd;dat = minimum time for valid sda output following scl low. [2] t vd;ack = time for acknowledgement signal from scl low to sda output low. table 54. i 2 c-bus timing characteristic v dd1 , v dd2 , v dd3 = 2.5 v to 5.5 v; v ss1 = 0 v; v lcd = 4.0 v to 12.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. all timing values are valid within the operating supply vo ltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss1 to v dd1 . symbol parameter conditions min typ max unit f scl scl frequency - - 400 khz t buf bus free time between a stop and start condition 1.3 - - ? s t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t vd;dat data valid time [1] --0 . 9 ? s t vd;ack data valid acknowledge time [2] --0 . 9 ? s t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s t f fall time of both sda and scl signals - - 0.3 ? s t r rise time of both sda and scl signals - - 0.3 ? s t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - ? s t w(spike) spike pulse width - - 50 ns fig 57. i 2 c-bus timing 6 & / 6 ' $ w + ' 6 7 $ w 6 8 ' $ 7 w + ' ' $ 7 w i w % 8 ) w 6 8 6 7 $ w / 2 : w + , * + w 9 ' $ & . d d d w 6 8 6 7 2 s u r w r f r o 6 7 $ 5 7 f r q g l w l r q 6 e l w 0 6 % $ e l w $ e l w 5 : d f n q r z o h g j h $ 6 7 2 3 f r q g l w l r q 3 i 6 & / w u w 9 ' ' $ 7 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 84 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 14.3 spi-bus timi ng characteristics [1] no load value; bus will be held up by bus capacitance; use rc time constant with application values. table 55. spi-bus timing characteristics v dd1 , v dd2 , v dd3 = 2.5 v to 5.5 v; v ss1 = 0 v; v lcd = 4.0 v to 12.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. all timing values are valid within the operating supply vo ltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss1 to v dd1 . symbol parameter conditions min max unit pin scl f clk(scl) scl clock frequency - 3.0 mhz t scl scl time 333 - ns t clk(h) clock high time 100 - ns t clk(l) clock low time 150 - ns t r rise time for scl signal - 100 ns t f fall time for scl signal - 100 ns pin ce t su(ce_n) ce_n set-up time 30 - ns t h(ce_n) ce_n hold time 30 - ns t rec(ce_n) ce_n recovery time 30 - ns pin sdi/sdain t su set-up time set-up time for sdi data 30 - ns t h hold time hold time for sdi data 30 - ns pin sdo t d(r)sdo sdo read delay time c l = 100 pf - 150 ns t dis(sdo) sdo disable time [1] -5 0n s t t(sdi-sdo) transition time from sdi to sdo to avoid bus conflict 0 - ns pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 85 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver fig 58. spi-bus timing d d d 5 : 6 $ 5 $ e e e e e e e e e 6 ' , 6 ' 2 6 ' 2 k l j k = k l j k = 6 ' , 6 & / & ( z u l w h u h d g w f o n / w i w k & ( b 1 w u h f & ( b 1 w g l v 6 ' 2 w g 5 6 ' 2 w u w k w v x w f o n + w v x & ( b 1 w f o n 6 & / w w 6 ' , 6 ' 2 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 86 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 15. application information 15.1 ito layout recommendations for esd/emc robustness in cog applications the crucial factor for gaining an emc and esd robust application is the quality of the vss1 line. ? to get an emc/esd robust ito/glass layout, the r ito(vss1) has to be kept as low as possible. ? in the most common ap plications vss1 will be connected to the pins t1, t2, a0, a1, osc, sa0, sa1 and ifs (in the case of usin g the spi interface) by using a very wide ito connection ? if possible, the ito connection of vss1 s hould be made wide, for example by fanning out the other connections ? when the display is enabled, the charge and discharge caused by display activity affects the vss1 line. this causes a dynam ic current in the vss1 line which means that dynamic voltage peaks in the vss1 line may interfere wit h the low voltage part of the pca8538. therefore a low r ito(vss1) is also important for an improved noise immunity of the pca8538 especially at high v lcd values (v lcd >10v). ? a low r ito(vss1) will also improve the communication stability with the microcontroller by reducing the effects of local ground (vss1) bounce caused by high sdaack currents. ? it should be considered that vss1 is internally connec ted to the ic substrate, therefore noise on the vss1 line w ill cause noise inside the ic. figure 59 and figure 60 are showing the recommended ito connections for a cog layout according to the interface type use. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 87 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver (1) r ito ? 100 ? . (2) r ito ? 50 ? . (3) r ito ? 200 ? . fig 59. recommended ito connections for the i 2 c interface 3 & $ 8 % 3 9 / & ' 6 ( 1 6 ( 7 9 / & ' , 1 9 / & ' 2 8 7 , 7 2 i r l o f r q q h f w r u 9 6 6 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 6 6 7 % 3 % 3 % 3 7 7 $ $ 7 , ) 6 6 $ 6 $ & ( 5 6 7 6 ' 2 % 3 % 3 % 3 & / . 6 < 1 & 6 < 1 & 6 ' , 6 ' $ , 1 6 & / % 3 6 ' $ 2 8 7 2 6 & 7 % 3 6 6 6 6 6 [ \ % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 6 d d d 9 / & ' 9 6 6 9 ' ' 5 6 7 6 & / 6 ' , 6 ' $ , 1 6 ' $ 2 8 7 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 88 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver (1) r ito ? 100 ? . (2) r ito ? 50 ? . (3) r ito ? 200 ? . fig 60. recommended ito connections for the spi interface 3 & $ 8 % 3 9 / & ' 6 ( 1 6 ( 7 9 / & ' , 1 9 / & ' 2 8 7 , 7 2 i r l o f r q q h f w r u 9 6 6 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 6 6 7 % 3 % 3 % 3 7 7 $ $ 7 , ) 6 6 $ 6 $ & ( 5 6 7 6 ' 2 % 3 % 3 % 3 & / . 6 < 1 & 6 < 1 & 6 ' , 6 ' $ , 1 6 & / % 3 6 ' $ 2 8 7 2 6 & 7 % 3 6 6 6 6 6 [ \ % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 6 d d d 9 / & ' 9 6 6 9 ' ' 5 6 7 & ( 6 & / 6 ' 2 6 ' , pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 89 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 15.2 cascaded operation in large display configurations, up to four pca8538 can be distinguis hed on the same bus by using the 2-bit hardware device addresses (a0 and a1). 15.2.1 wiring backplane and segment outputs when the cascaded pca8538 are synchronized, they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other pca8538 of the cascade contribute additional segment output s. the backplanes can either be connected together to enhance the drive ca pability or some can be left open-circuit (suc h as the ones from the slave in figure 61 and figure 62 ) or just some of the master and some of the slave will be taken to facilitate the layout of the display. table 56. addressing cascaded pca8538 pin a1 pin a0 device 0 0 0 (master) 011 (slave) 102 (slave) 113 (slave) pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 90 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver (1) is master (osc and a0 connected to v ss1 ). (2) is slave (osc and a0 connected to v dd1 ). fig 61. cascaded configuration with two pca8538 with external v lcd and internal clock 3 & $ v h j p h q w v e d f n s o d q h v 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 ' ' $ $ 9 6 6 9 6 6 9 6 6 9 / & ' h [ w 9 / & ' 2 8 7 9 / & ' 6 ( 1 6 ( 9 / & ' , 1 3 & $ + 2 6 7 0 & 8 / & ' 3 $ 1 ( / v h j p h q w v e d f n s o d q h v r s h q f l u f x l w 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 ' ' $ $ 9 6 6 9 6 6 9 6 6 9 / & ' h [ w 9 / & ' 2 8 7 9 / & ' 6 ( 1 6 ( 9 / & ' , 1 6 3 , r u , & e x v 9 ' ' 9 ' ' 9 6 6 6 < 1 & 6 < 1 & 6 < 1 & 6 < 1 & 2 6 & 2 6 & & / . & / . d d d pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 91 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 15.2.2 device synchronization the sync0 and sync1 lines are provided to maintain the correct synchronization between all cascaded pca8538. (sync1 must not be connected when using an externally supplied v lcd .)this synchronization is guaranteed after the power-on reset (por). sync0 and sync1 are organized as input/output pins. both, the internally generated clock frequency or, alternatively, an externally supplied clock signal can be used in cascaded applications. in cascaded applications that use the intern al clock, the master pca8538 with device address a[1:0] = 00 must have the osc pin connected to v ss1 and the coe bit is set logic 1, so that this device uses its internal clock to generate a clock signal at the clk pin. (1) is master (a0 connected to v ss1 ). (2) is slave (a0 connected to v dd1 ). fig 62. cascaded configuration with two pca8538 with internal v lcd and external clock 3 & $ v h j p h q w v e d f n s o d q h v 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 ' ' $ $ 9 6 6 9 6 6 9 6 6 9 / & ' 2 8 7 9 / & ' 6 ( 1 6 ( 9 / & ' , 1 3 & $ + 2 6 7 0 & 8 / & ' 3 $ 1 ( / v h j p h q w v e d f n s o d q h v r s h q f l u f x l w 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 ' ' $ $ 9 6 6 9 6 6 9 6 6 9 / & ' 2 8 7 9 / & ' 6 ( 1 6 ( 9 / & ' , 1 6 3 , r u , & e x v 9 ' ' 9 ' ' 9 6 6 6 < 1 & 6 < 1 & 6 < 1 & 6 < 1 & 2 6 & 2 6 & & / . & / . & / . & / . d d d 9 / & ' pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 92 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver the other pca8538 devices are hav ing the osc pin connected to v dd1 , meaning that these devices are ready to receive an external clock signal which is provided by the master device with subaddress a[1:0] = 00. if the master is providing the clock signal to th e slave devices, care must be taken that the sending of display enable or disable will be rece ived by both, the master and the slaves at the same time. when the display is disabled, th e output from pin clk is disabled too. the disconnection of the clock may result in a dc component for the display. in cascaded applications that use an exte rnal clock, all devices have the osc pin connected to v dd1 and thus an external clk being provided for the system (all devices connected to the same external clk). 15.2.3 display data the storage of display data is determined by the contents of the device address register (see section 8.2.3 on page 10 ). storage is allowed only wh en the content of the device address register matches with the hardware device address applied to the pins a0 and a1. if the content of the device address regi ster and the hardware device address do not match, data storage is inhibited but the data pointer is incremented as if data storage had taken place. the hardware device address mu st not be changed while the device is being accessed on the interface. 15.2.4 data read only when the content of the device address register (see section 8.2.3 on page 10 ) matches with the hardware device address app lied to the pins a0 and a1, the temperature or device status readout (see section 8.2.7 on page 12 ) is activated. if the content of the device address register and the hardware device address do not match, the data output pin (sda or sdo) of the device is in 3-state. with this, bus conflicts and incorrect reading is prevented. pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 93 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 16. test information 16.1 quality information this product has been qualified in accordance with the automotive electronics council (aec) standard q100 - failure mechanism based stress test qualification for integrated circuits , and is suitable for use in automotive applications. (1) master. (2) slave. a. i 2 c interface (1) master. (2) slave. b. spi interface fig 63. cascade configuration for data reading d d d 6 ' $ 6 & / 3 & $ 6 & / 6 ' $ , 1 6 ' $ 2 8 7 3 & $ 6 & / 6 ' $ , 1 6 ' $ 2 8 7 k l j k o r z k l j k = 6 $ 6 $ 6 $ 6 $ 9 6 6 6 & / 6 ' , 6 ' 2 6 & / 6 ' , 6 ' 2 k l j k o r z k l j k = 6 & / 6 ' , d d d & ( & ( 6 ' 2 & ( 3 & $ 3 & $ pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 94 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 17. bare die outline fig 64. bare die outline of PCA8538UG 5 h i h u h q f h v 2 x w o l q h y h u v l r q ( x u r s h d q s u r m h f w l r q , v v x h g d w h , ( & - ( ' ( & - ( , 7 $ 3 & $ 8 s f d x b g r % d u h g l h e x p s v 3 & $ 8 < g h w d l o ; h e / g h w d l o < $ $ 6 & \ [ ' ( ; h $ 1 r w h v ' l h p d u n l q j f r g h 3 & ) l j x u h q r w g u d z q w r v f d o h 3 & $ 8 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 95 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver table 57. dimensions of pca8538u original dimensions are in mm. unit (mm) a a 1 a 2 b d e e e 1 l max -0.018------- nom 0.40 0.015 0.38 0.03 5.88 1.20 0.045 0.158 0.09 min -0.012------- table 58. bump locations all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 64 . symbol pin coordinates pitch symbol pin coordinates pitch x (m) y (m) x (m) x (m) y (m) x (m) com8 1 ? 2847.5 ? 495 - s101 126 2846.7 495 - 2 ? 2802.5 ? 495 45 127 2801.7 495 45 3 ? 2757.5 ? 495 45 s100 128 2756.7 495 45 com7 4 ? 2712.5 ? 495 45 s99 129 2711.7 495 45 5 ? 2667.5 ? 495 45 s98 130 2666.7 495 45 com6 6 ? 2622.5 ? 495 45 s97 131 2621.7 495 45 7 ? 2577.5 ? 495 45 s96 132 2576.7 495 45 com5 8 ? 2532.5 ? 495 45 s95 133 2531.7 495 45 9 ? 2487.5 ? 495 45 s94 134 2486.7 495 45 com4 10 ? 2442.5 ? 495 45 s93 135 2441.7 495 45 11 ? 2397.5 ? 495 45 s92 136 2396.7 495 45 vlcdin 12 ? 2352.5 ? 495 45 s91 137 2351.7 495 45 13 ? 2307.5 ? 495 45 s90 138 2306.7 495 45 14 ? 2262.5 ? 495 45 s89 139 2261.7 495 45 15 ? 2217.5 ? 495 45 s88 140 2216.7 495 45 vlcdsense 16 ? 2172.5 ? 495 45 s87 141 2171.7 495 45 17 ? 2127.5 ? 495 45 s86 142 2126.7 495 45 18 ? 2082.5 ? 495 45 s85 143 2081.7 495 45 vlcdout 19 ? 2037.5 ? 495 45 s84 144 1975.7 495 106 20 ? 1992.5 ? 495 45 s83 145 1930.7 495 45 21 ? 1 947.5 ? 495 45 s82 146 1885.7 495 45 22 ? 1902.5 ? 495 45 s81 147 1840.7 495 45 t4 23 ? 1857.5 ? 495 45 s80 148 1795.7 495 45 24 ? 1812.5 ? 495 45 s79 149 1750.7 495 45 25 ? 1767.5 ? 495 45 s78 150 1705.7 495 45 t3 26 ? 1722.5 ? 495 45 s77 151 1660.7 495 45 27 ? 1677.5 ? 495 45 s76 152 1615.7 495 45 28 ? 1632.5 ? 495 45 s75 153 1570.7 495 45 29 ? 1587.5 ? 495 45 s74 154 1525.7 495 45 30 ? 1542.5 ? 495 45 s73 155 1480.7 495 45 t5 31 ? 1497.5 ? 495 45 s72 156 1435.7 495 45 32 ? 1452.5 ? 495 45 s71 157 1390.7 495 45 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 96 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver t6 33 ? 1407.5 ? 495 45 s70 158 1345.7 495 45 34 ? 1362.5 ? 495 45 s69 159 1300.7 495 45 vss2 35 ? 1317.5 ? 495 45 s68 160 1255.7 495 45 36 ? 1272.5 ? 495 45 s67 161 1210.7 495 45 37 ? 1227.5 ? 495 45 s66 162 1165.7 495 45 38 ? 1182.5 ? 495 45 s65 163 1120.7 495 45 39 ? 1137.5 ? 495 45 s64 164 1075.7 495 45 40 ? 1092.5 ? 495 45 s63 165 1030.7 495 45 41 ? 1047.5 ? 495 45 s62 166 985.7 495 45 42 ? 1002.5 ? 495 45 s61 167 940.7 495 45 43 ? 957.5 ? 495 45 s60 168 895.7 495 45 44 ? 912.5 ? 495 45 s59 169 850.7 495 45 vss3 45 ? 867.5 ? 495 45 s58 170 805.7 495 45 46 ? 822.5 ? 495 45 s57 171 760.7 495 45 47 ? 777.5 ? 495 45 s56 172 715.7 495 45 48 ? 732.5 ? 495 45 s55 173 670.7 495 45 vss1 49 ? 687.5 ? 495 45 s54 174 625.7 495 45 50 ? 642.5 ? 495 45 s53 175 580.7 495 45 51 ? 597.5 ? 495 45 s52 176 535.7 495 45 52 ? 552.5 ? 495 45 s51 177 490.7 495 45 53 ? 5 07.5 ? 495 45 com0 178 382.1 495 108.6 54 ? 462.5 ? 495 45 179 337.1 495 45 55 ? 417.5 ? 495 45 com1 180 292.1 495 45 56 ? 372.5 ? 495 45 181 247.1 495 45 57 ? 327.5 ? 495 45 com2 182 202.1 495 45 t1 58 ? 282.5 ? 495 45 183 157.1 495 45 59 ? 237.5 ? 495 45 com3 184 112.1 495 45 t2 60 ? 192.5 ? 495 45 185 67.1 495 45 61 ? 147.5 ? 495 45 com4 186 22.1 495 45 a0 62 ? 102.5 ? 495 45 187 ? 22.9 495 45 63 ? 57.5 ? 495 45 com5 188 ? 67.9 495 45 a1 64 ? 12.5 ? 495 45 189 ? 112.9 495 45 65 32.5 ? 495 45 com6 190 ? 157.9 495 45 ifs 66 77.5 ? 495 45 191 ? 202.9 495 45 67 122.5 ? 495 45 com7 192 ? 247.9 495 45 osc 68 167.5 ? 495 45 193 ? 292.9 495 45 69 212.5 ? 495 45 com8 194 ? 337.9 495 45 table 58. bump locations ?continued all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 64 . symbol pin coordinates pitch symbol pin coordinates pitch x (m) y (m) x (m) x (m) y (m) x (m) pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 97 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver sa0 70 257.5 ? 495 45 com8 195 ? 382.9 495 45 71 302.5 ? 495 45 s50 196 ? 491.5 495 108.6 sa1 72 347.5 ? 495 45 s49 197 ? 536.5 495 45 73 392.5 ? 495 45 s48 198 ? 581.5 495 45 vdd1 74 437.5 ? 495 45 s47 199 ? 626.5 495 45 75 482.5 ? 495 45 s46 200 ? 671.5 495 45 76 527.5 ? 495 45 s45 201 ? 716.5 495 45 77 572.5 ? 495 45 s44 202 ? 761.5 495 45 78 617.5 ? 495 45 s43 203 ? 806.5 495 45 vdd3 79 662.5 ? 495 45 s42 204 ? 851.5 495 45 80 707.5 ? 495 45 s41 205 ? 896.5 495 45 81 752.5 ? 495 45 s40 206 ? 941.5 495 45 82 797.5 ? 495 45 s39 207 ? 986.5 495 45 vdd2 83 842.5 ? 495 45 s38 208 ? 1031.5 495 45 84 887.5 ? 495 45 s37 209 ? 1076.5 495 45 85 932.5 ? 495 45 s36 210 ? 1121.5 495 45 86 977.5 ? 495 45 s35 211 ? 1166.5 495 45 87 1022.5 ? 495 45 s34 212 ? 1211.5 495 45 88 1067.5 ? 495 45 s33 213 ? 1256.5 495 45 89 1112.5 ? 495 45 s32 214 ? 1301.5 495 45 90 1157.5 ? 495 45 s31 215 ? 13 46.5 495 45 ce 91 1202.5 ? 495 45 s30 216 ? 1391.5 495 45 92 1247.5 ? 495 45 s29 217 ? 1436.5 495 45 clk 93 1292.5 ? 495 45 s28 218 ? 1481.5 495 45 94 1337.5 ? 495 45 s27 219 ? 1526.5 495 45 95 1382.5 ? 495 45 s26 220 ? 1571.5 495 45 sync1 96 1427.5 ? 495 45 s25 221 ? 1616.5 495 45 97 1472.5 ? 495 45 s24 222 ? 1661.5 495 45 98 1517.5 ? 495 45 s23 223 ? 1706.5 495 45 sync0 99 1562.5 ? 495 45 s22 224 ? 1751.5 495 45 100 1607.5 ? 495 45 s21 225 ? 1796.5 495 45 101 1652.5 ? 495 45 s20 226 ? 1841.5 495 45 rst 102 1697.5 ? 495 45 s19 227 ? 1886.5 495 45 103 1742.5 ? 495 45 s18 228 ? 1931.5 495 45 sdi/sdain 104 1787.5 ? 495 45 s17 229 ? 1976.5 495 45 105 1832.5 ? 495 45 s16 230 ? 2082.5 495 106 106 1877.5 ? 495 45 s15 231 ? 2127.5 495 45 table 58. bump locations ?continued all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 64 . symbol pin coordinates pitch symbol pin coordinates pitch x (m) y (m) x (m) x (m) y (m) x (m) pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 98 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver the alignment marks are shown in table 59 . sdaout 107 1922.5 ? 495 45 s14 232 ? 2172.5 495 45 108 1967.5 ? 495 45 s13 233 ? 2217.5 495 45 109 2012.5 ? 495 45 s12 234 ? 2262.5 495 45 110 2057.5 ? 495 45 s11 235 ? 2307.5 495 45 111 2102.5 ? 495 45 s10 236 ? 2352.5 495 45 sdo 112 2147.5 ? 495 45 s9 237 ? 2397.5 495 45 113 2192.5 ? 495 45 s8 238 ? 2442.5 495 45 scl 114 2237.5 ? 495 45 s7 239 ? 2487.5 495 45 115 2282.5 ? 495 45 s6 240 ? 2532.5 495 45 116 2327.5 ? 495 45 s5 241 ? 2577.5 495 45 com3 117 2485.2 ? 495 157.7 s4 242 ? 2622.5 495 45 118 2530.2 ? 495 45 s3 243 ? 2667.5 495 45 com2 119 2575.2 ? 495 45 s2 244 ? 2712.5 495 45 120 2620.2 ? 495 45 s1 245 ? 2757.5 495 45 com1 121 2665.2 ? 495 45 s0 246 ? 2802.5 495 45 122 2710.2 ? 495 45 247 ? 2847.5 495 45 com0 123 2755.2 ? 495 45 - - - - 124 2800.2 ? 495 45 - - - - 125 2845.2 ? 495 45 - - - - fig 65. alignment marks table 59. alignment marking all x/y coordinates represent the position of the ref point (see figure 65 ) with respect to the center (x/y = 0) of the chip; see figure 64 . symbol size ( ? m) x ( ? m) y (? m) s1 90 ? 90 ? 2375 15 c1 90 ? 90 2312 15 table 58. bump locations ?continued all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 64 . symbol pin coordinates pitch symbol pin coordinates pitch x (m) y (m) x (m) x (m) y (m) x (m) d d d 5 ( ) 5 ( ) & 6 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 99 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] pressure of diamond head: 10 g to 50 g. 18. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. table 60. gold bump hardness type number min max unit [1] PCA8538UG/2da/q1 60 120 hv pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 100 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 19. packing information 19.1 tray information schematic drawing, not drawn to scale . top side view. for dimensions see table 61 . tray has pockets on both, top side and bottom side. the ic is stored with the active side up. to get the active side down, turn the tray. fig 66. tray details of pca8538u + g h w d l o < g h w d l o ; < ; ( 0 1 2 / * ) ( ) - $ . 6 ( & 7 , 2 1 $ $ % ' $ & $ ' l p h q v l r q v l q p p d d d [ \ \ [ g l h pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 101 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver table 61. description of tray details tray details are shown in figure 66 . tray details dimensions abcdef ghj kl mnounit 8 2.5 5.978 1.298 76 68 56 6.75 10 62.5 4.2 2.6 3.2 0.6 mm number of pockets x direction y direction 826 the orientation of the ic in a pocket with active side up is indicated by t he position of pin 1 with respect to the chamfer on the upper left corner of the tray. fig 67. die alignment in the tray d d d s l q xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 102 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 20. appendix 20.1 lcd segment driver selection table 62. selection of lcd segment drivers type name number of elements at mux v dd (v) v lcd (v) f fr (hz) v lcd (v) charge pump v lcd (v) temperature compensat. t amb ( ?c) interface package aec- q100 1:1 1:2 1:3 1:4 1:6 1:8 1:9 pca8561ahn [5] 18 36 54 72 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 i 2 chvqfn32y pca8561bhn [5] 18 36 54 72 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 spi hvqfn32 y pcf8566ts 24 48 72 96 - - - 2.5 to 6 2.5 to 6 69 n n ? 40 to 85 i 2 c vso40 n pcf85162t 32 64 96 128 - - - 1.8 to 5.5 2.5 to 6.5 82 n n ? 40 to 85 i 2 ctssop48n pca85162t 32 64 96 128 - - - 1.8 to 5.5 2.5 to 8 110 n n ? 40 to 95 i 2 ctssop48y pca85262att 32 64 96 128 - - - 1.8 to 5.5 2.5 to 8 200 n n ? 40 to 105 i 2 ctssop48y pcf8551att [5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 128 [1] nn ? 40 to 85 i 2 ctssop48n pcf8551btt [5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 128 [1] nn ? 40 to 85 spi tssop48 n pca8551att [5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 i 2 ctssop48y pca8551btt [5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 spi tssop48 y pcf85176t 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 82 n n ? 40 to 85 i 2 ctssop56n pca85176t 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 110 n n ? 40 to 95 i 2 ctssop56y pca85276att 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 200 n n ? 40 to 105 i 2 ctssop56y pcf85176h 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 82 n n ? 40 to 85 i 2 ctqfp64n pca85176h 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 82 n n ? 40 to 95 i 2 ctqfp64y pcf8553att [5] 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 128 [1] nn ? 40 to 85 i 2 ctssop56n pcf8553btt [5] 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 128 [1] nn ? 40 to 85 spi tssop56 n pca8553att [5] 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 i 2 ctssop56y pca8553btt [5] 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 spi tssop56 y pca8546att ---176---1.8to5.52.5to960to300 [1] nn ? 40 to 95 i 2 ctssop56y pca8546btt ---176---1.8to5.52.5to960to300 [1] nn ? 40 to 95 spi tssop56 y pca8547aht [5] 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 95 i 2 ctqfp64y pca8547bht [5] 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 95 spi tqfp64 y pcf85134hl 60 120 180 240 - - - 1.8 to 5.5 2.5 to 6.5 82 n n ? 40 to 85 i 2 clqfp80n pca85134h 60 120 180 240 - - - 1.8 to 5.5 2.5 to 8 82 n n ? 40 to 95 i 2 clqfp80y xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 103 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [1] can be selected by command. [2] can be selected by pin configuration. pca8543ahl 60 120 - 240 - - - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 105 i 2 clqfp80y pcf8545att ---176252320-1.8to5.52.5to5.560to300 [1] nn ? 40 to 85 i 2 ctssop56n pcf8545btt ---176252320-1.8to5.52.5to5.560to300 [1] nn ? 40 to 85 spi tssop56 n pcf8536at [4] ---176252320-1.8to5.52.5to960to300 [1] nn ? 40 to 85 i 2 ctssop56n pcf8536bt [4] ---176252320-1.8to5.52.5to960to300 [1] nn ? 40 to 85 spi tssop56 n pca8536at [4] ---176252320-1.8to5.52.5to960to300 [1] nn ? 40 to 95 i 2 ctssop56y pca8536bt [4] ---176252320-1.8to5.52.5to960to300 [1] nn ? 40 to 95 spi tssop56 y pcf8537ah 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 85 i 2 ctqfp64n pcf8537bh 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 85 spi tqfp64 n pca8537ah 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 95 i 2 ctqfp64y pca8537bh 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 95 spi tqfp64 y pca9620h 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 105 i 2 clqfp80y pca9620u 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy [3] ? 40 to 105 i 2 c bare die y pcf8552dug [5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 128 [1] nn ? 40 to 85 i 2 c, spi bare die n pca8552dug [5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 i 2 c, spi bare die y pcf8576du 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 n n ? 40 to 85 i 2 c bare die n pcf8576eug 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 n n ? 40 to 85 i 2 c bare die n pca8576fug 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 200 n n ? 40 to 105 i 2 c bare die y pcf85133u 80 160 240 320 - - - 1.8 to 5.5 2.5 to 6.5 82, 110 [2] nn ? 40 to 85 i 2 c bare die n pca85133u 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 82, 110 [2] nn ? 40 to 95 i 2 c bare die y pca85233u 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 150, 220 [2] nn ? 40 to 105 i 2 c bare die y pca8530dug [5] 102 204 - 408 - - - 2.5to5.5 4to12 45to300 [1] yy [3] ? 40 to 105 i 2 c, spi bare die y pcf85132u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90 [1] nn ? 40 to 85 i 2 c bare die n pca85132u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90 [1] nn ? 40 to 95 i 2 c bare die y pca85232u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 117 to 176 [1] nn ? 40 to 95 i 2 c bare die y pcf8538ug 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300 [1] yy [3] ? 40 to 85 i 2 c, spi [2] bare die n PCA8538UG 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300 [1] yy [3] ? 40 to 105 i 2 c, spi [2] bare die y table 62. selection of lcd segment drivers ?continued type name number of elements at mux v dd (v) v lcd (v) f fr (hz) v lcd (v) charge pump v lcd (v) temperature compensat. t amb ( ?c) interface package aec- q100 1:1 1:2 1:3 1:4 1:6 1:8 1:9 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 104 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver [3] extra feature: temperature sensor. [4] extra feature: 6 pwm channels. [5] in development. pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 105 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 21. abbreviations table 63. abbreviations acronym description aec automotive electronics council cog chip-on-glass dc direct current eprom erasable programmable read-only memory esd electrostatic discharge hbm human body model i 2 c inter-integrated circuit bus ic integrated circuit ito indium tin oxide lcd liquid crystal display lsb least significant bit mcu microcontroller unit mm machine model msb most significant bit msl moisture sensitivity level mux multiplexer otp one time programmable por power-on reset rc resistance-capacitance ram random access memory rms root mean square scl serial clock line sda serial data line smd surface mount device spi serial peripheral interface va vertical alignment pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 106 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 22. references [1] an10170 ? design guidelines for cog modules with nxp monochrome lcd drivers [2] an10439 ? wafer level chip size package [3] an10853 ? esd and emc sensitivity of ic [4] an10706 ? handling bare die [5] an11267 ? emc and system level esd design guidelines for lcd drivers [6] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [7] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [8] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [9] jesd78 ? ic latch-up test [10] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [11] r_10015 ? chip-on-glass (cog) ? a cost-effective and reliable technology for lcd displays, white paper [12] snv-fa-01-02 ? marking formats integrated circuits [13] um10204 ? i 2 c-bus specification and user manual [14] um10569 ? store and transport requirements pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 107 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 23. revision history table 64. revision history document id release date data sheet status change notice supersedes pca8538 v.3 20131125 product data sheet - pca8538 v.2 modifications: ? fixed typos pca8538 v.2 20130924 product data sheet - pca8538 v.1 pca8538 v.1 20130322 objective data sheet - - pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 108 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 24. legal information 24.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 24.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 24.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 109 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are da ta sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 24.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 25. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 110 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 26. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . . .3 table 3. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 5. commands of pca8538 . . . . . . . . . . . . . . . . . .8 table 6. initialize command bit description . . . . . . . . . .10 table 7. otp-refresh - otp-refresh command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 8. device-address - device address command bit description . . . . . . . . . . . . . . . . . . . . . . . . .10 table 9. sync1_pin - sync1 pin configuration command bit description. . . . . . . . . . . . . . . . . . 11 table 10. clock-out-ctrl - cl k pin input/output switch command bit description . . . . . . . . . . . . . . . . . 11 table 11. read-select - status read select command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 12. status-readout - status and temperature read command bit description . . . . . . . . . . . . . . . . .12 table 13. clear-reset-flag - clear-reset-flag command bit description . . . . . . . . . . . . . . . . . . . . . . . . .13 table 14. charge-pump-ctrl - charge pump control command bit description . . . . . . . . . . . . . . . . .14 table 15. set-v lcd - set-v lcd command bit description .14 table 16. set-bias-mode - set bias mode command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 17. temperature-ctrl - temperature measurement control command bit descripti on . . . . . . . . . . .16 table 18. tc-set - v lcd temperature compensation set command bit description . . . . . . . . . . . . . . . . .17 table 19. tc-slope - v lcd temperature compensation slope command bit description . . . . . . . . . . . .18 table 20. set-mux-mode - set multiplex drive mode command bit description . . . . . . . . . . . . . . . . .19 table 21. inversion-mode - inversion mode command bit description . . . . . . . . . . . . . . . . . . . . . . . . .19 table 22. display-ctrl - display on and off switch command bit description . . . . . . . . . . . . . . . . .20 table 23. frame-frequency - frame frequency select command bit description . . . . . . . . . . . . . . . . .21 table 24. clock and frame frequency values . . . . . . . . .22 table 25. write-display-data - write display data command bit description . . . . . . . . . . . . . . . . .23 table 26. input-bank-select - input bank select command bit description . . . . . . . . . . . . . . . . . . . . . . . . .23 table 27. output-bank-sele ct - output bank select command bit description . . . . . . . . . . . . . . . . .24 table 28. data-pointer-x and data-pointer-y - set data pointer command bit description . . . . . . . . . . .24 table 29. reset state of pca8538 . . . . . . . . . . . . . . . . .25 table 30. selection of possible display configurations . . .32 table 31. parameters of v lcd generation . . . . . . . . . . . .35 table 32. output resistance of the charge pump . . . . . . .37 table 33. temperature regions . . . . . . . . . . . . . . . . . . . .42 table 34. temperature coefficients. . . . . . . . . . . . . . . . . .43 table 35. calculation of the temperature compensated value vt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 36. lcd drive modes: su mmary of characteristics 44 table 37. mapping of output pins and corresponding output signals with respect to the multiplex driving mode . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 38. layout topology of output pins and corresponding output signals with respect to the multiplex driving mode . . . . . . . . . . . . . . . 56 table 39. bit scheme used to illustrate the ram filling patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 40. ram filling in static drive mode . . . . . . . . . . . . 59 table 41. ram filling in 1:2 multiplex drive mode . . . . . . 59 table 42. ram filling in 1:4 multiplex drive mode . . . . . . 60 table 43. ram filling in 1:6 multiplex drive mode . . . . . . 60 table 44. ram filling in 1:8 multiplex drive mode . . . . . . 61 table 45. ram filling in 1:9 multiplex drive mode . . . . . . 61 table 46. control byte description . . . . . . . . . . . . . . . . . 65 table 47. i 2 c slave address byte . . . . . . . . . . . . . . . . . . . 68 table 48. r/w -bit description. . . . . . . . . . . . . . . . . . . . . . 68 table 49. serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 50. subaddress byte definition. . . . . . . . . . . . . . . . 70 table 51. limiting values . . . . . . . . . . . . . . . . . . . . . . . . 74 table 52. static characteristics . . . . . . . . . . . . . . . . . . . . 75 table 53. general dynamic characteristics . . . . . . . . . . . 82 table 54. i 2 c-bus timing characteristic . . . . . . . . . . . . . . 83 table 55. spi-bus timing characteristics . . . . . . . . . . . . . 84 table 56. addressing cascaded pca8538 . . . . . . . . . . . 89 table 57. dimensions of pca8538u . . . . . . . . . . . . . . . 95 table 58. bump locations . . . . . . . . . . . . . . . . . . . . . . . . 95 table 59. alignment marking . . . . . . . . . . . . . . . . . . . . . . 98 table 60. gold bump hardness . . . . . . . . . . . . . . . . . . . . 99 table 61. description of tray details. . . . . . . . . . . . . . . . 101 table 62. selection of lcd segment drivers . . . . . . . . 102 table 63. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 105 table 64. revision history . . . . . . . . . . . . . . . . . . . . . . . 107 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 111 of 113 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 27. figures fig 1. block diagram of pca8538 . . . . . . . . . . . . . . . . . .4 fig 2. pinning diagram of PCA8538UG . . . . . . . . . . . . . .5 fig 3. recommended start-up sequence when using the internal charge pump and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 fig 4. recommended start-up sequence when using an external supplied v lcd and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 fig 5. recommended start-up sequence when using the internal charge pump and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 fig 6. recommended start-up sequence when using an external supplied v lcd and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 fig 7. recommended power-down sequence for minimum power-down current when using the internal charge pump and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 fig 8. recommended power-down sequence when using an external supplied v lcd and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 fig 9. recommended power-down sequence when using the internal charge pump and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 fig 10. recommended power-down sequence when using an external supplied v lcd and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 fig 11. example of display types suitable for pca8538 .32 fig 12. typical system c onfiguration if using the internal v lcd generation and i 2 c-bus . . . . . . . . .33 fig 13. typical system c onfiguration if using the external v lcd and spi-bus . . . . . . . . . . . . . . . . .33 fig 14. v lcd generation including temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .35 fig 15. v lcd programming of pca8538 (assuming vt[8:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 fig 16. charge pump model (used to characterize the driving strength) . . . . . . . . . . . . . . . . . . . . . . . . . .36 fig 17. charge pump driving capability with v dd2 = 3.0 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 fig 18. charge pump driving capability with v dd2 = 5.0 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 fig 19. v lcd with respect to i load at v dd2 = 3 v . . . . . . . .39 fig 20. v lcd with respect to i load at v dd2 = 5 v . . . . . . . .39 fig 21. temperature measurement block with digital temperature filter . . . . . . . . . . . . . . . . . . . . . . . . .40 fig 22. temperature measurement delay . . . . . . . . . . . .41 fig 23. example of segmented temperature coefficients.42 fig 24. electro-optical ch aracteristic: relative transmission curve of the liquid . . . . . . . . . . . . . .46 fig 25. static drive mode waveforms, line inversion mode (n = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 fig 26. waveforms for the 1:2 multiplex drive mode, 1 2 bias, line inversion mode (n = 1) . . . . . . . . . . .48 fig 27. waveforms for the 1:2 multiplex drive mode, 1 3 bias, line inversion mode (n = 1) . . . . . . . . . . .49 fig 28. waveforms for the 1:4 multiplex drive mode, 1 3 bias, line inversion mode (n = 1). . . . . . . . . . . 50 fig 29. waveforms for 1:6 multiplex drive mode, 1 3 bias, line inversion mode (n = 1). . . . . . . . . . . 51 fig 30. waveforms for 1:6 multiplex drive mode, 1 4 bias, line inversion mode (n = 1). . . . . . . . . . . 52 fig 31. waveforms for 1:8 multiplex drive mode, 1 4 bias, line inversion mode (n = 1). . . . . . . . . . . 53 fig 32. waveforms for 1:9 multiplex drive mode with 1 4 bias and line inversion mode (n = 1). . . . . . . . 54 fig 33. waveforms for 1:9 multiplex drive mode with 1 4 bias and frame inversion mode . . . . . . . . . . . 55 fig 34. display ram bitmap and bank definition . . . . . . 62 fig 35. example of bank selection in 1:4 multiplex mode 63 fig 36. example of the in put-bank-select and the output-bank-select command with multiplex drive mode 1:4 . . . . . . . . . . . . . . . . . . . . . . . . . . 63 fig 37. control byte format . . . . . . . . . . . . . . . . . . . . . . . 65 fig 38. i 2 c-bus - bit transfer . . . . . . . . . . . . . . . . . . . . . . 66 fig 39. i 2 c-bus - definition of start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 fig 40. i 2 c-bus - system configuration . . . . . . . . . . . . . . 67 fig 41. acknowledgement on the i 2 c-bus. . . . . . . . . . . . 68 fig 42. i 2 c-bus protocol - write mode . . . . . . . . . . . . . . . 69 fig 43. i 2 c-bus protocol - read mode . . . . . . . . . . . . . . . 69 fig 44. spi-bus protocol - data transfer overview . . . . . . 70 fig 45. spi-bus example. . . . . . . . . . . . . . . . . . . . . . . . . 71 fig 46. spi-bus protocol - read example. . . . . . . . . . . . . 71 fig 47. spi-bus protocol - write example . . . . . . . . . . . . 71 fig 48. device protection diagram . . . . . . . . . . . . . . . . . 72 fig 49. typical i dd1 with respect to temperature . . . . . . . 78 fig 50. typical i dd2 with respect to temperature . . . . . . . 78 fig 51. typical i dd3 with respect to temperature . . . . . . . 79 fig 52. typical i dd(lcd) with respect to temperature . . . . 79 fig 53. typical v lcd variation with respect to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 fig 54. typical frame frequency variation with respect to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 80 fig 55. measurement temperature variation with respect to temperature . . . . . . . . . . . . . . . . . . . . 81 fig 56. driver timing waveforms . . . . . . . . . . . . . . . . . . . 82 fig 57. i 2 c-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 fig 58. spi-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 85 fig 59. recommended ito connections for the i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 fig 60. recommended ito connections for the spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 fig 61. cascaded configuration with two pca8538 with external v lcd and internal clock . . . . . . . . . . . . . 90 fig 62. cascaded configuration with two pca8538 with internal v lcd and external clock . . . . . . . . . . . . . 91 fig 63. cascade configuration for data reading . . . . . . . 93 fig 64. bare die outline of pca8 538ug . . . . . . . . . . . . . 94 fig 65. alignment marks . . . . . . . . . . . . . . . . . . . . . . . . . 98 fig 66. tray details of pca8538u. . . . . . . . . . . . . . . . . 100 fig 67. die alignment in the tray . . . . . . . . . . . . . . . . . . 101 pca8538 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 25 november 2013 112 of 113 continued >> nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver 28. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 8 8.1 commands of pca8538 . . . . . . . . . . . . . . . . . . 8 8.2 general control commands . . . . . . . . . . . . . . 10 8.2.1 command: initialize . . . . . . . . . . . . . . . . . . . . 10 8.2.2 command: otp-refresh . . . . . . . . . . . . . . . . . 10 8.2.3 command: device-address . . . . . . . . . . . . . . 10 8.2.4 command: sync1_pin . . . . . . . . . . . . . . . . . 11 8.2.5 command: clock-out-ctrl . . . . . . . . . . . . . . . . 11 8.2.6 command: read-select . . . . . . . . . . . . . . . . . 12 8.2.7 command: status-readout . . . . . . . . . . . . . . . 12 8.2.8 command: clear-reset-flag . . . . . . . . . . . . . . 13 8.3 charge pump and lcd bias control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.3.1 command: charge-pump-ctrl . . . . . . . . . . . . . 14 8.3.2 command: set-v lcd . . . . . . . . . . . . . . . . . . . . 14 8.3.3 command: set-bias-mode . . . . . . . . . . . . . . . 15 8.4 temperature compensation control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.4.1 command: temper ature-ctrl . . . . . . . . . . . . . . 16 8.4.2 command: tc-set . . . . . . . . . . . . . . . . . . . . . 17 8.4.3 command: tc-slope . . . . . . . . . . . . . . . . . . . 18 8.5 display control commands . . . . . . . . . . . . . . . 19 8.5.1 command: set-mux-mode . . . . . . . . . . . . . . 19 8.5.2 command: inversion-mode . . . . . . . . . . . . . . 19 8.5.2.1 line inversion mode (driving scheme a). . . . . 20 8.5.2.2 frame inversion mode (driving scheme b) . . . 20 8.5.3 command: display-ctrl . . . . . . . . . . . . . . . . . . 20 8.6 clock and frame frequency command . . . . . . 21 8.6.1 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.3 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.4 command: frame-frequency . . . . . . . . . . . . . 21 8.7 display ram commands . . . . . . . . . . . . . . . . 23 8.7.1 command: write-display-data . . . . . . . . . . . . 23 8.7.2 bank select commands . . . . . . . . . . . . . . . . . 23 8.7.2.1 command: input-bank-select . . . . . . . . . . . . . 23 8.7.2.2 command: output-bank-se lect . . . . . . . . . . . 24 8.7.3 commands: data-pointer-x and data-pointer-y . . . . . . . . . . . . . . . . . . . . . . . . 24 8.8 start-up and shut-down . . . . . . . . . . . . . . . . . 25 8.8.1 power-on reset (por) . . . . . . . . . . . . . . . . . 25 8.8.2 reset pin function . . . . . . . . . . . . . . . . . . . . . 26 8.8.3 recommended start-up sequences . . . . . . . . 27 8.8.4 recommended power-down sequences . . . . 29 8.9 possible display configurations . . . . . . . . . . . 32 8.10 lcd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.10.1 v lcd pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.10.2 external v lcd supply . . . . . . . . . . . . . . . . . . . 34 8.10.3 internal v lcd generation . . . . . . . . . . . . . . . . 34 8.10.3.1 v lcd programming . . . . . . . . . . . . . . . . . . . . . 34 8.10.3.2 v lcd driving capability . . . . . . . . . . . . . . . . . . 36 8.10.4 temperature meas urement and temperature compensation of v lcd . . . . . . . . . . . . . . . . . . 40 8.10.4.1 temperature readout . . . . . . . . . . . . . . . . . . . 40 8.10.4.2 temperature adjustment of the v lcd . . . . . . . 41 8.10.5 lcd voltage selector . . . . . . . . . . . . . . . . . . . 43 8.10.5.1 electro-optical performanc e . . . . . . . . . . . . . . 45 8.10.6 lcd drive mode waveforms. . . . . . . . . . . . . . 47 8.10.6.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . 47 8.10.6.2 1:2 multiplex drive mode . . . . . . . . . . . . . . . . 48 8.10.6.3 1:4 multiplex drive mode . . . . . . . . . . . . . . . . 50 8.10.6.4 1:6 multiplex drive mode . . . . . . . . . . . . . . . . 51 8.10.6.5 1:8 multiplex drive mode . . . . . . . . . . . . . . . . 53 8.10.6.6 1:9 multiplex drive mode . . . . . . . . . . . . . . . . 54 8.11 backplane outputs . . . . . . . . . . . . . . . . . . . . . 56 8.11.1 driving strength on the backplanes . . . . . . . . 56 8.12 segment outputs . . . . . . . . . . . . . . . . . . . . . . 57 8.13 display register . . . . . . . . . . . . . . . . . . . . . . . 57 8.14 display ram . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.14.1 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.14.1.1 data pointer in cascade configuration . . . . . . 58 8.14.2 ram filling . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.14.2.1 ram filling in static drive mode . . . . . . . . . . . 59 8.14.2.2 ram filling in 1:2 multiplex drive mode . . . . . 59 8.14.2.3 ram filling in 1:4 multiplex drive mode . . . . . 60 8.14.2.4 ram filling in 1:6 multiplex drive mode . . . . . 60 8.14.2.5 ram filling in 1:8 multiplex drive mode . . . . . 61 8.14.2.6 ram filling in 1:9 multiplex drive mode . . . . . 61 8.14.3 bank selection . . . . . . . . . . . . . . . . . . . . . . . . 62 8.14.3.1 input-bank-select . . . . . . . . . . . . . . . . . . . . . . 64 8.14.3.2 output-bank-select. . . . . . . . . . . . . . . . . . . . . 64 9 bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 control byte and register selection . . . . . . . . 65 9.2 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . 66 nxp semiconductors pca8538 automotive 102 x 9 chip-on-glass lcd segment driver ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 25 november 2013 document identifier: pca8538 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 9.2.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.2 start and stop conditions . . . . . . . . . . . . . 66 9.2.3 system configuration . . . . . . . . . . . . . . . . . . . 67 9.2.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 68 9.2.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.7 i 2 c-bus slave address . . . . . . . . . . . . . . . . . . 68 9.2.8 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 69 9.3 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.3.1 data transmission . . . . . . . . . . . . . . . . . . . . . . 70 10 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 72 11 safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 74 13 static characteristics. . . . . . . . . . . . . . . . . . . . 75 14 dynamic characteristics . . . . . . . . . . . . . . . . . 82 14.1 general dynamic characteristics. . . . . . . . . . . 82 14.2 i 2 c-bus timing characteristics . . . . . . . . . . . . . 83 14.3 spi-bus timing characteristics . . . . . . . . . . . . 84 15 application information. . . . . . . . . . . . . . . . . . 86 15.1 ito layout recommendations for esd/emc robustness in cog applications . . . . . . . . . . . 86 15.2 cascaded operation . . . . . . . . . . . . . . . . . . . . 89 15.2.1 wiring backplane and segment outputs . . . . . 89 15.2.2 device synchronization. . . . . . . . . . . . . . . . . . 91 15.2.3 display data . . . . . . . . . . . . . . . . . . . . . . . . . . 92 15.2.4 data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16 test information . . . . . . . . . . . . . . . . . . . . . . . . 93 16.1 quality information . . . . . . . . . . . . . . . . . . . . . 93 17 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 94 18 handling information. . . . . . . . . . . . . . . . . . . . 99 19 packing information . . . . . . . . . . . . . . . . . . . 100 19.1 tray information . . . . . . . . . . . . . . . . . . . . . . 100 20 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 20.1 lcd segment driver selection. . . . . . . . . . . . 102 21 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 105 22 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 23 revision history . . . . . . . . . . . . . . . . . . . . . . . 107 24 legal information. . . . . . . . . . . . . . . . . . . . . . 108 24.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 108 24.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 24.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 24.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 109 25 contact information. . . . . . . . . . . . . . . . . . . . 109 26 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 27 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 28 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 |
Price & Availability of PCA8538UG
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